Datasheet

AD7142
Rev. A | Page 17 of 72
Low Power Mode CDC Conversion Sequence Time with
Delay
The frequency of each CDC conversion operating in the low
power automatic wake-up mode is controlled by using the
LP_CONV_DELAY register located at Address 0x000[3:2], in
addition to the registers listed in
Table 1 0. This feature provides
some flexibility for optimizing the conversion time to meet
system requirements vs. AD7142 power consumption.
For example, maximum power savings is achieved when the
LP_CONV_DELAY register is set to 3. With a setting of 3, the
AD7142 automatically wakes up, performing a conversion
every 800 ms.
Table 11. LP_CONV_DELAY Settings
LP_CONV_DELAY Bits Delay Between Conversions
00 200 ms
01 400 ms
10 600 ms
11 800 ms
Figure 27 shows a simplified timing example of the low power
CDC conversion time. As shown, the low power CDC conversion
time is set by t
CONV_FP
and the LP_CONV_DELAY register.
05702-016
CONVERSION
SEQUENCE N
CDC
CONVERSION
CONVERSION
SEQUENCE N+1
LP_CONV_DELAY
t
CONV_FP
t
CONV_LP
Figure 27. Low Power Mode CDC Conversion Sequence Time
CDC CONVERSION RESULTS
Certain high resolution sensors require the host to read back
the CDC conversion results for processing. The registers
required for host processing are located in the Bank 3 registers.
The host processes the data readback from these registers using
a software algorithm, to determine position information.
In addition to the results registers in the Bank 3 registers, the
AD7142 provides the 16-bit CDC output data directly, starting
at Address 0x00B of Bank 1. Reading back the CDC 16-bit
conversion data register allows for customer-specific application
data processing.