Datasheet

Data Sheet AD7091R
Rev. 0 | Page 5 of 20
TIMING SPECIFICATIONS
V
DD
= 2.75 V to 5.25 V, V
DRIVE
= 1.65 V to 5.25 V, T
A
= −40°C to +125°C, unless otherwise noted.
1
Table 2.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
50 MHz max Frequency of serial read clock
t
1
8 ns max Delay from the end of a conversion until SDO three-state is disabled
t
2
7 ns max Data access time after SCLK falling edge
t
3
0.4 t
SCLK
ns min SCLK high pulse width
t
4
3 ns min SCLK to data valid hold time
t
5
0.4 t
SCLK
ns min SCLK low pulse width
t
6
15 ns max SCLK falling edge to SDO high impedance
t
7
10 ns min
CONVST
pulse width
t
8
650 ns max Conversion time
t
9
6 ns min
CS
low time before the end of a conversion
t
10
18 ns max
Delay from
CS
until SDO three-state is disabled
t
11
8 ns min
CS
high time before the end of a conversion
t
12
8
ns min
Delay from the end of a conversion until
CS
falling edge
t
13
50 ms typ Power-up time with internal reference
2
100 µs max Power-up time with external reference
t
QUIET
50 ns min Time between last SCLK edge and next
CONVST
pulse
1
Sample tested during initial release to ensure compliance.
2
With a 2.2 µF reference capacitor.