Datasheet

Data Sheet AD7091R
Rev. 0 | Page 17 of 20
WITHOUT BUSY INDICATOR
To operate the AD7091R without the BUSY indicator feature
enabled, a conversion should first be started. A high-to-low
transition on
CONVST
initiates a conversion. This puts the
track-and-hold into hold mode and samples the analog input
at this point. If the user does not want the AD7091R to enter
power-down mode,
CONVST
should be taken high before the
end of the conversion. A conversion requires 650 ns to complete.
When the conversion process is finished, the track-and-hold
goes back to track mode. To prevent the BUSY indicator feature
from becoming enabled, ensure that
CS
is pulled high before
the end of the conversion.
The data is shifted out of the device as a 12-bit word under the
control of SCLK and
CS
. The MSB (Bit DB11) is clocked out on the
falling edge of
CS
. DB10 to DB0 are shifted out on the subsequent
falling edges of SCLK. The 12
th
falling SCLK edge returns SDO
to a high impedance state. After all the data is clocked out, pull
CS
high again. SCLK should idle low in this mode to ensure that
the MSB is not lost. Data is propagated on SCLK falling edges
and is valid on both the rising and falling edges of the next SCLK.
The timing diagram for this operation is shown in Figure 28.
If another conversion is required, pull
CONVST
low and repeat
the read cycle.
Figure 28. Serial Port Timing Without BUSY Indicator
THREE-STATE
THREE-STATE
CS
SCLK
1 5 122 3 4
DB11
DB10 DB9 DB2 DB1
t
2
t
3
t
5
t
6
DB8 DB7
SDO
CONVST
EOC
10 11
t
10
t
QUIET
t
7
t
8
t
4
t
11
DB0
t
12
10494-027
NOTES
1. EOC IS THE END OF A CONVERSION.