Datasheet

AD7091R Data Sheet
Rev. 0 | Page 16 of 20
SERIAL INTERFACE
The AD7091R serial interface consists of four signals: SDO,
SCLK,
CONVST
, and
CS
. The serial interface is used for
accessing data from the result register and controlling the
modes of operation of the device. SCLK is the serial clock input
for the device, and SDO data transfers take place with respect to
this SCLK. The
CONVST
signal is used to initiate the
conversion process and to select the mode of operation of the
AD7091R (see the Modes of Operation section).
CS
is used to
frame the data. The falling edge of
CS
takes the SDO line out of a
high impedance state. A rising edge on
CS
returns the SDO to a
high impedance state.
The logic level of
CS
at the end of a conversion determines whether
the BUSY indicator feature is enabled. This feature affects the
propagation of the MSB with respect to
CS
and SCLK.
WITH BUSY INDICATOR
When the BUSY indicator feature is enabled, the SDO pin can
be used as an interrupt signal to indicate that a conversion is
complete. The connection diagram for this configuration is
shown in Figure 26. Note that a pull-up resistor to V
DRIVE
is
required on the SDO pin. This allows the host to detect when
the SDO pin exits the three-state condition after the end of a
conversion. In this mode, 13 SCLK cycles are required: 12 clock
cycles to propagate out the data and an additional clock cycle to
return the SDO pin to the three-state condition.
To enable the BUSY indicator feature, a conversion should first
be started. A high-to-low transition on
CONVST
initiates a
conversion. This puts the track-and-hold into hold mode and
samples the analog input at this point. If the user does not want
the AD7091R to enter power-down mode,
CONVST
should be
taken high before the end of the conversion. A conversion
requires 650 ns to complete. When the conversion process is
finished, the track-and-hold goes back to track mode. Before
the end of a conversion, pull
CS
low to enable the BUSY
indicator feature.
The conversion result is shifted out of the device as a 12-bit
word under the control of SCLK and the logic state of
CS
at the
end of a conversion. At the end of a conversion, SDO is driven
low. SDO remains low until the MSB (DB11) of the conversion
result is clocked out on the first falling edge of SCLK. DB10 to
DB0 are shifted out on the subsequent falling edges of SCLK.
The 13
th
SCLK falling edge returns SDO to a high impedance
state. Data is propagated on SCLK falling edges and is valid on
both the rising and falling edges of the next SCLK. The timing
diagram for this mode is shown in Figure 27.
If another conversion is required, pull
CONVST
low again and
repeat the read cycle.
Figure 26. Connection Diagram with BUSY Indicator
Figure 27. Serial Port Timing with BUSY Indicator
DATA IN
IRQ
CLK
CONVERT
V
DRIVE
DIGITAL HOST
100kΩ
CONVST
SCLK
SDO
CS
AD7091R
CS1
10494-025
THREE-STATE
THREE-STATE
CS
SCLK
1
5
12
2
3 4
DB11 DB10 DB9 DB2 DB1
DB0
t
2
t
4
t
3
t
5
t
6
DB8 DB7
SDO
CONVST
EOC
NOTES
1. EOC IS THE END OF A CONVERSION.
t
1
10 11
t
9
t
QUIET
t
7
t
8
13
10494-026