Datasheet

AD7091R Data Sheet
Rev. 0 | Page 14 of 20
MODES OF OPERATION
The mode of operation of the AD7091R is selected by controlling
the logic state of the
CONVST
signal when a conversion is
complete.
The logic level of the
CONVST
pin at the end of a conversion
determines whether the AD7091R remains in normal mode or
enters power-down mode (see the Normal Mode and Power-
Down Mode sections). Similarly, if the device is already in
power-down mode,
CONVST
controls whether the device
returns to normal mode or remains in power-down mode.
These modes of operation provide flexible power management
options, allowing optimization of the ratio of the power dissipation
to the throughput rate for different application requirements.
Normal Mode
The normal mode of operation is intended to achieve the fastest
throughput rate performance. Users do not have to worry about
power-up times because the AD7091R remains fully powered at
all times. Figure 29 shows the general timing diagram of the
AD7091R in normal mode.
In this mode, the conversion is initiated on the falling edge
of
CONVST
, as described in the Serial Interface s ecti on. To
ensure that the part remains fully powered up at all
times,
CONVST
must return high after t
7
and remain high until
the conversion is complete. At the end of a conversion (denoted
as EOC in Figure 27), the logic state of
CONVST
is tested.
To read back data stored in the conversion result register, wait until
the conversion is complete, and then pull
CS
low. The conversion
data is subsequently clocked out on the SDO pin (see Figure 29).
Because the output shift register is 12 bits wide, data is shifted
out of the device as a 12-bit word under the control of the serial
clock input (SCLK). After reading back the data, the user can
pull
CONVST
low again to start another conversion after the
t
QUIET
time has elapsed.
Power-Down Mode
The power-down mode of operation is intended for use in
applications where slower throughput rates and lower power
consumption are required. In this mode, the ADC can be
powered down either between each conversion or between a
series of conversions performed at a high throughput rate, with
the ADC powered down for relatively long durations between
these bursts of several conversions. When the AD7091R is in
power-down mode, the serial interface remains active even
though all analog circuitry, including the internal voltage
reference, is powered down.
To enter power-down mode, pull
CONVST
low and keep it low
until the end of a conversion (denoted as EOC in Figure 30). After
the conversion is complete, the logic level of the
CONVST
pin is
tested. If the
CONVST
signal is logic low at this point, the part
enters power-down mode.
The serial interface of the AD7091R is functional in power-
down mode; therefore, users can read back the conversion
result after the part enters power-down mode.
To exit this mode of operation and power up the AD7091R,
pull
CONVST
high at any time. On the rising edge of
CONVST
,
the device begins to power up. The internal circuitry of the
AD7091R requires 100 μs to power up from power-down mode.
If the internal reference is used, the reference capacitor must be
fully recharged before accurate conversions are possible.
To start the next conversion after exiting power-down mode,
operate the interface as described in the Normal Mode section.
POWER CONSUMPTION
The two modes of operation for the AD7091Rnormal mode
and power-down mode (see the Modes of Operation section for
more information)—produce different power vs. throughput
rate performances. Using a combination of normal mode and
power-down mode achieves the optimum power performance.
To calculate the overall power consumption, the I
DRIVE
current
should also be taken into consideration. Figure 16 shows the I
DRIVE
current at various supply voltages. Figure 23 and Figure 24 show
the power consumption for V
DRIVE
with various throughput rates.
Improved power consumption for the AD7091R can be achieved
by carefully selecting the V
DD
and V
DRIVE
supply voltages and the
SDO line capacitance (see Figure 15 and Figure 16).
Normal Mode
With a 3 V V
DD
supply and a throughput rate of 1 MSPS, the I
DD
current consumption for the part in normal operational mode is
349 μA (composed of 21.6 μA of static current and 327.4 μA of
dynamic current during conversion). The dynamic current
consumption is directly proportional to the throughput rate.
The following example calculates the power consumption of
AD7091R when operating in normal mode with a 500 kSPS
throughput rate and a 3 V supply.
The dynamic conversion time contributes 491 μW to the overall
power dissipation as follows:
((500 kSPS/1 MSPS) × 327.4 μA) × 3 V = 491 μW
The contribution to the total power dissipated by the normal
mode static operation is
21.6 μA × 3 V = 65 μW
Therefore, the total power dissipated at 500 kSPS is
491 μW + 65 μW = 556 μW