Datasheet

AD676
REV. A
–9–
CONTINUOUS CONVERSION
For maximum throughput rate, the AD676 can be operated in a
continuous convert mode (see Figure 2b). This is accomplished
by utilizing the fact that SAMPLE will no longer be ignored af-
ter BUSY goes LOW, so an acquisition may be initiated even
during the HIGH time of the 17th CLK pulse for maximum
throughput rate while enabling full settling of the sample/hold
circuitry. If SAMPLE is already HIGH when BUSY goes LOW
at the end of a conversion, then an acquisition is immediately
initiated and t
S
and t
C
start from that time. Data from the previ-
ous conversion may be latched up to t
SD
before BUSY goes
LOW or t
OD
after the rising edge of the 17th clock pulse. How-
ever, it is preferred that latching occur on or after the falling
edge of BUSY.
Care must he taken to adhere to the minimum/maximum timing
requirements in order to preserve conversion accuracy.
GENERAL CONVERSION GUIDELINES
During signal acquisition and conversion, care should be taken
with the logic inputs to avoid digital feedthrough noise. It is pos-
sible to run CLK continuously, even during the sample period.
However, CLK edges during the sampling period, and especially
when SAMPLE goes LOW, may inject noise into the sampling
process. The AD676 is tested with no CLK cycles during the
sampling period. The BUSY signal can be used to prevent the
clock from running during acquisition, as illustrated in Figure 3.
In this circuit BUSY is used to reset the circuitry which divides
the system clock down to provide the AD676 CLK. This serves
to interrupt the clock until after the input signal has been ac-
quired, which has occurred when BUSY goes HIGH. When the
conversion is completed and BUSY goes LOW, the circuit in
Figure 3 truncates the 17th CLK pulse width which is tolerable
because only its rising edge is critical.
5
2 10
7
1
7
12
9
4
11
12.288MHz
SYSTEM
CLOCK
CLK
74HC175
2D
1Q
CLR
3D
2Q3Q
1D
BUSY
CLK
AD676
9
SAMPLE
2
8
9
12
6
13
1
1QD
74HC393
1CLR
2CLR
2QD
2QC
1CLK
2CLK
Figure 3.
Figure 3 also illustrates the use of a counter (74HC393) to de-
rive the AD676 SAMPLE command from the system clock
when a continuous convert mode is desirable. Pin 9 (2QC) pro-
vides a 96 kHz sample rate for the AD676 when used with a
12.288 MHz system clock. Alternately, Pin 8 (2QD) could be
used for a 48 kHz rate.
If a continuous clock is used, then the user must avoid CLK
edges at the instant of disconnecting V
IN
which occurs at the
falling edge of SAMPLE (see t
SC
specification). The duty cycle
of CLK may vary, but both the HIGH (t
CH
) and LOW (t
CL
)
phases must conform to those shown in the timing specifica-
tions. The internal comparator makes its decisions on the rising
edge of CLK. To avoid a negative edge transition disturbing the
comparator’s settling, t
CL
should be at least half the value of t
CLK
.
To also avoid transitions disturbing the internal comparator’s
settling, it is not recommended that the SAMPLE pin change
state toward the end of a CLK cycle.
During a conversion, internal dc error terms such as comparator
voltage offset are sampled, stored on internal capacitors and
used to correct for their corresponding errors when needed. Be-
cause these voltages are stored on capacitors, they are subject to
leakage decay and so require refreshing. For this reason there is
a maximum conversion time t
C
(1000 µs). From the time
SAMPLE goes HIGH to the completion of the 17th CLK pulse,
no more than 1000 µs should elapse for specified performance.
However, there is no restriction to the maximum time between
conversions.
Output coding for the AD676 is twos complement, as shown in
Table I. By inverting the MSB, the coding can be converted to
offset binary. The AD676 is designed to limit output coding in
the event of out-of-range inputs.
Table I. Output Coding
V
IN
Output Code
>Full Scale 011 . . . 11
Full Scale 011 . . . 11
Full Scale – 1 LSB 011 . . . 10
Midscale + 1 LSB 000 . . . 01
Midscale 000 . . . 00
Midscale – 1 LSB 111 . . . 11
–Full Scale + 1 LSB 100 . . . 01
–Full Scale 100 . . . 00
<–Full Scale 100 . . . 00