Datasheet

AD673
REV. A
–3–
ORDERING GUIDE
Temperature Relative
Model Range Accuracy Package Option
1
AD673JN 0°C to +70°C ±1/2 LSB max Plastic DIP (N-20)
AD673JD 0°C to +70°C ±1/2 LSB max Ceramic DIP (D-20)
AD673SD
2
–55°C to +125°C ±1/2 LSB max Ceramic DIP (D-20)
AD673JP 0°C to +70°C ±1/2 LSB max PLCC (P-20A)
NOTES
1
D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier.
2
For details on grade and package offering screened in accordance with MIL-STD-883, refer to the
Analog Devices Military Products Databook .
ABSOLUTE MAXIMUM RATINGS
V+ to Digital Common . . . . . . . . . . . . . . . . . . . . . 0 V to +7 V
V– to Digital Common . . . . . . . . . . . . . . . . . . . 0 V to –16.5 V
Analog Common to Digital Common . . . . . . . . . . . . . . . ±1 V
Analog Input to Analog Common . . . . . . . . . . . . . . . . . ±15 V
Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V+
Digital Outputs (High Impedance State) . . . . . . . . . . 0 V to V+
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW
FUNCTIONAL DESCRIPTION
A block diagram of the AD673 is shown in Figure 1. The posi-
tive CONVERT pulse must be at least 500 ns wide.
DR goes
high within 1.5 µs after the leading edge of the convert pulse in-
dicating that the internal logic has been reset. The negative edge
of the CONVERT pulse initiates the conversion. The internal
8-bit current output DAC is sequenced by the integrated injec-
tion logic (I
2
L) successive approximation register (SAR) from its
most significant bit to least significant bit to provide an output
current which accurately balances the input signal current
through the 5 kΩ resistor. The comparator determines whether
the addition of each successively weighted bit current causes the
DAC current sum to be greater or less than the input current; if
the sum is more, the bit is turned off. After testing all bits, the
SAR contains a 8-bit binary code which accurately represents
the input signal to within (0.05% of full scale).
BURIED ZENER REF
COMP-
ARATOR
ANALOG
IN
DB7
V+ V–
DIGITAL
COMMON
CONVERT
INT
CLOCK
8-BIT
SAR
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MSB
LSB
ANALOG
COMMON
BIPOLAR
OFFSET
CONTROL
DATA
READY
AD673
5k
DATA
ENABLE
8-BIT
CURRENT
OUTPUT
DAC
Figure 1. AD673 Functional Block Diagram
The SAR drives DR low to indicate that the conversion is com-
plete and that the data is available to the output buffers.
DATA
ENABLE can then be activated to enable the 8-bits of data de-
sired.
DATA ENABLE should be brought high prior to the next
conversion to place the output buffers in the high impedance state.
The temperature compensated buried Zener reference provides
the primary voltage reference to the DAC and ensures excellent
stability with both time and temperature. The bipolar offset in-
put controls a switch which allows the positive bipolar offset
current (exactly equal to the value of the MSB less 1/2 LSB) to
be injected into the summing (+) node of the comparator to off-
set the DAC output. Thus the nominal 0 V to +10 V unipolar
input range becomes a –5 V to +5 V range. The 5 kΩ thin-film
input resistor is trimmed so that with a full-scale input signal, an
input current will be generated which exactly matches the DAC
output with all bits on.
UNIPOLAR CONNECTION
The AD673 contains all the active components required to per-
form a complete A/D conversion. Thus, for many applications,
all that is necessary is connection of the power supplies (+5 V
and –12 V to –15 V), the analog input and the convert pulse.
However, there are some features and special connections which
should be considered for achieving optimum performance. The
functional pinout is shown in Figure 2.
The standard unipolar 0 V to +10 V range is obtained by short-
ing the bipolar offset control pin (Pin 16) to digital common
(Pin 17).
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD673
* PINS 1 & 2 ARE INTERNALLY
CONNECTED TO TEST POINTS AND SHOULD BE LEFT FLOATING
NC
*
DIGITAL COMMON
DATA READY
NC
DATA ENABLE
NC *
LSB DB0
DB1
ANALOG IN
ANALOG COMMON
BIPOLAR OFFSET
DB2
DB3
DB4
DB5
DB6
MSB DB7
V+
CONVERT
V–
PIN 1
IDENTIFIER
Figure 2. AD673 Pin Connections