Datasheet

AD669
REV. A
–3–
TIMING CHARACTERISTICS
V
CC
= +15 V, V
EE
= –15 V, V
LL
= +5 V, V
HI
= 2.4 V, V
LO
= 0.4 V
Limit Limit
Limit –408C to –558C to
Parameter +258C +858C +1258C Units
(Figure la)
t
CS
40 50 55 ns min
t
LI
40 50 55 ns min
t
DS
30 35 40 ns min
t
DH
10 10 15 ns min
t
LH
90 110 120 ns min
t
LW
40 45 45 ns min
(Figure lb)
t
LOW
130 150 165 ns min
t
HIGH
40 45 45 ns min
t
DS
120 140 150 ns min
t
DH
10 10 15 ns min
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical
test. Results from those tests are used to calculate outgoing quality levels. All
min and max specifications are guaranteed. Those shown in boldface are tested
on all production units.
AC PERFORMANCE CHARACTERISTICS
Parameter Limit Units Test Conditions/Comments
Output Settling Time 13 µs max 20 V Step, T
A
= +25°C
(Time to ±0.0008% FS 8 µs typ 20 V Step, T
A
= +25°C
with 2 kΩ, 1000 pF Load) 10 µs typ 20 V Step, T
MIN
≤ T
A
≤ T
MAX
6 µs typ 10 V Step, T
A
= +25°C
8 µs typ 10 V Step, T
MIN
≤ T
A
≤ T
MAX
2.5 µs typ 1 LSB Step, T
MIN
≤ T
A
≤ T
MAX
Total Harmonic Distortion + Noise
A, B, S Grade 0.009 % max 0 dB, 1001 Hz; Sample Rate = 100 kHz; T
A
= +25°C
A, B, S Grade 0.07 % max –20 dB, 1001 Hz; Sample Rate = 100 kHz; T
A
= +25°C
A, B, S Grade 7.0 % max –60 dB, 1001 Hz; Sample Rate = 100 kHz; T
A
= +25°C
Signal-to-Noise Ratio 83 dB min T
A
= +25°C
Digital-to-Analog Glitch Impulse 15 nV-s typ DAC Alternately Loaded with 8000H and 7FFFH
Digital Feedthrough 2 nV-s typ DAC Alternately Loaded with 0000H and FFFFH; CS High
Output Noise Voltage 120 nV/√
Hz typ Measured at V
OUT
, 20 V Span; Excludes Reference
Density (1 kHz – 1 MHz)
Reference Noise 125 nV/√Hz typ Measured at REF OUT
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed. Those shown in boldface are tested on all production units.
(With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise
Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested.
T
MIN
≤ T
A
≤ T
MAX
, V
CC
= +15 V, V
EE
= –15 V, V
LL
= +5 V except where noted.)
DATA
LDAC
t
DS
t
DH
CS
t
LW
t
LH
L1
t
CS
t
L1
Figure 1a. AD669 Level Triggered Timing Diagram
DATA
t
DS
t
DH
CS AND/OR
L1, LDAC
TIE CS AND/OR
L1 TO GROUND OR TOGETHER WITH LDAC
t
LOW
t
HIGH
Figure 1b. AD669 Edge Triggered Timing Diagram