Datasheet

AD664
REV.
–11–
OUTPUT DATA
Two types of outputs may be obtained from the internal data
registers of the AD664 chip, mode select and DAC input code
data. Readback data may be in the same forms in which it can
be entered; 4-, 8-, and 12-bit wide words (12 bits only for
28-pin versions).
DAC Data Readback
DAC input code readback data is obtained by setting the address
of the DAC (DS0, DS1) and Quads (
QS0, QS1, QS2) on the
address pins and bringing the
RD and CS pins low. The timing
diagram for a DAC code readback operation appears in Figure 20.
Figure 20a. DAC Input Code Readback
25°CT
MIN
to T
MAX
SYMBOL MIN (ns) MIN (ns)
t
AS
00
t
RS
00
t
DV
150 180
t
DF
60 75
t
AH
00
t
RH
00
Figure 20b. DAC Input Code Readback Timing
Mode Data Readback
Mode data is read back in a similar fashion. By setting
MS, QS0,
QS1, RD and CS low while setting TR and RST high, the mode
select word is presented to the I/O port pins. Figure 21 shows the
timing diagram for a readback of the mode select data register.
Figure 21a. Mode Data Readback
258CT
MIN
to T
MAX
SYMBOL MIN (ns) MIN (ns)
t
AS
00
t
MS
00
t
DV
150 180
t
DF
60 75
t
AH
00
t
MH
00
Figure 21b. DAC Mode Readback Timing
Fully transparent operation can be thought of as a simultaneous
load of data from Figure 9a where replacing
LS with TR causes
all 4 DACs to be loaded at once.
The Fully transparent mode is achieved by asserting lows on
QS0, QS1, QS2, TR and CS while keeping LS high in addition
to
MS and RB. Figure 18a illustrates the necessary timing rela-
tionships. Fully transparent operation will also work with
TR
tied low (enabled).
DATA INPUT/
OUTPUT BITS
t
TS
t
DS
t
QH
t
DH
t
QS
DATA VALID
TW
t
t
CH
1
LS
QS
TR
CS
Figure 18a. Fully Transparent Mode
258CT
MIN
to T
MAX
SYMBOL MIN (ns) MIN (ns)
t
AS
00
t
QS
00
t
TS
*0 0
t
TW
80 90
t
CH
90 110
t
DH
00
t
QH
00
*FOR t
TS
> 0, THE WIDTH OF TR MUST BE
INCREASED BY THE SAME AMOUNT THAT
t
TS
IS GREATER THAN 0 ns.
Figure 18b. Fully Transparent Mode Timing
Partially transparent operation can be thought of as preloading
the first rank in Figure 10a without requiring the additional
CS
pulse from Figure 11.
The partially transparent mode is achieved by setting
CS, QS0,
QS1, QS2, LS, and TR low while keeping RD and MS high.
The address of the transparent DAC is asserted on DS0 and
DS1. Figure 19a illustrates the necessary timing relationships.
Partially transparent operation will also work with
TR tied low
(enabled).
DATA INPUT/
OUTPUT BITS
ADDRESS
QS0, QS1, QS2
DS0, DS1, LS
t
TS
t
AS
t
DH
DATA VALID
W
t
t
TH
TR
CS
ADDRESS VALID
t
AH
t
DS
Figure 19a. Partially Transparent
25°CT
MIN
to T
MAX
SYMBOL MIN (ns) MIN (ns)
t
DS
00
t
AS
00
t
TS
00
t
W
90 110
t
DH
15 15
t
AH
15 15
t
TH
15 15
Figure 19b. Partially Transparent Mode Timing
D