Datasheet

AD667
Model AD667A AD667B AD667S
Min Typ Max Min Typ Max Min Typ Max Units
DIGITAL INPUTS
Resolution 12 12 12 Bits
Logic Levels (TTL, Compatible, T
MIN
–T
MAX
)
1
V
IH
(Logic “l’’) +2.0 +5.5 +2.0 +5.5 +2.0 +5.5 V
V
IL
(Logic “0”) 0 +0.8 0 +0.8 0 +0.7 V
I
IH
(V
IH
= 5.5 V) 3 10 3 10 3 10 µA
I
IL
(V
IL
= 0.8 V) 1 5 1 5 1 5 µA
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error @ +25°C +1/4 61/2 ±1/8 61/4 ±1/8 61/2 LSB
T
A
= T
MIN
to T
MAX
±1/2 63/4 ±1/4 61/2 ±1/8 63/4 LSB
Differential Linearity Error @ +25°C ±1/2 63/4 ±1/4 61/2 ±1/4 63/4 LSB
T
A
= T
MIN
to T
MAX
Monotonicity Guaranteed Monotonicity Guaranteed Monotonicity Guaranteed LSB
Gain Error
2
±0.1 60.2 ±0.1 60.2 ±0.1 60.2 % FSR
3
Unipolar Offset Error
2
±1 62 ±1 62 ±1 62 LSB
Bipolar Zero
2
±0.05 60.1 ±0.05 60.1 ±0.05 60.1 % of FSR
DRIFT
Differential Linearity ±2 ±2 ±2 ppm of FSR/°C
Gain (Full Scale) T
A
= 25°C to T
MIN
or T
MAX
±5 ±30 ±5 ±15 ±15 630 ppm of FSR/°C
Unipolar Offset T
A
= 25°C to T
MIN
or T
MAX
±1 ±3 ±3 63 ppm of FSR/°C
Bipolar Zero T
A
= 25°C to T
MIN
or T
MAX
±5 ±10 ±10 610 ppm of FSR/°C
CONVERSION SPEED
Settling Time to ±0.01% of FSR for
FSR Change (2 kΩi500 pF Load)
with 10 kΩ Feedback 3 4 3 4 3 4 µs
with 5 kΩ Feedback 2 3 2 3 2 3 µs
For LSB Change 1 1 1 µs
Slew Rate 10 10 10 V/µs
ANALOG OUTPUT
Ranges
4
±2.5, ±5, ±10, ±2.5, ±5, ±10, ±2.5, ±5, ±10, V
+5, +10 +5, +10 +5, +10
Output Current ±5 ±5 ±5mA
Output Impedance (DC) 0.05 0.05 0.05 Ω
Short Circuit Current 40 40 40 mA
REFERENCE OUTPUT 9.90 10.00 10.10 9.90 10.00 10.10 9.90 10.00 10.10 V
External Current 0.1 1.0 0.1 1.0 1.0 mA
POWER SUPPLY SENSITIVITY
V
CC
= +11.4 V to +16.5 V dc 5 10 5 10 5 10 ppm of FS/%
V
EE
= –11.4 V to –16.5 V dc 5 10 5 10 5 10 ppm of FS/%
POWER SUPPLY REQUIREMENTS
Rated Voltages ±12, ±15 ±12, ±15 ±12, ±15 V
Range
4
611.4 616.5 611.4 616.5 611.4 616.5 V
Supply Current
+11.4 V to +16.5 V dc 8 12 8 12 8 12 mA
–11.4 V to –16.5 V dc 20 25 20 25 20 25 mA
TEMPERATURE RANGE
Specification –25 +85 –25 +85 –55 +125 °C
Storage –65 +150 –65 +150 –65 +150 °C
TIMING DIAGRAMS
WRITE CYCLE #1
(Load First Rank from Data Bus; A3 = 1)
WRITE CYCLE #2
(Load Second Rank from First Rank; A2, A1, A0 = 1)
REV. A
–3–