AD667–SPECIFICATIONS Model AD667J Typ Min DIGITAL INPUTS Resolution Logic Levels (TTL, Compatible, T MIN–TMAX)1 VIH (Logic “l’’) VIL (Logic “0”) IIH (VIH = 5.5 V) IIL (VIL = 0.8 V) (@ TA = +258C, 612 V, 615 V power supplies unless otherwise noted) Max Min AD667K Typ 12 +5.5 +0.8 10 5 +2.0 0 3 1 TRANSFER CHARACTERISTICS ACCURACY Linearity Error @ +25°C TA = TMIN to TMAX Differential Linearity Error @ +25°C TA = TMIN to TMAX Gain Error 2 Unipolar Offset Error 2 Bipolar Zero 2 +2.
AD667 Model Min DIGITAL INPUTS Resolution Logic Levels (TTL, Compatible, TMIN–TMAX)1 VIH (Logic “l’’) VIL (Logic “0”) IIH (VIH = 5.5 V) IIL (VIL = 0.8 V) TRANSFER CHARACTERISTICS ACCURACY Linearity Error @ +25°C TA = TMIN to TMAX Differential Linearity Error @ +25°C TA = TMIN to TMAX Gain Error2 Unipolar Offset Error 2 Bipolar Zero2 +2.0 0 3 1 REFERENCE OUTPUT External Current ±2 ±5 ±1 ±5 3 2 1 TEMPERATURE RANGE Specification Storage Min ±5 +2.0 0 3 1 ±2 ±5 4 3 3 2 1 ± 2.
AD667 PIN CONNECTIONS PLCC, LCC DIP from the ideal analog output (a straight line drawn from 0 to FS – 1 LSB) for any bit combination. The AD667 is laser trimmed to 1/4 LSB (0.006% of FS) maximum error at +25°C for the K and B versions and 1/2 LSB for the J, A and S versions.
AD667 ANALOG CIRCUIT CONNECTIONS Internal scaling resistors provided in the AD667 may be connected to produce bipolar output voltage ranges of ±10, ±5 or ±2.5 V or unipolar output voltage ranges of 0 V to +5 V or 0 V to +10 V. Gain and offset drift are minimized in the AD667 because of the thermal tracking of the scaling resistors with other device components. Connections for various output voltage ranges are shown in Table I. Figure 3.
AD667 Small resistors may be added to the feedback resistors in order to accomplish small modifications in the scaling. For example, if a 10.24 V full scale is desired, a 140 Ω 1% low TC metal-film resistor can be added in series with the internal (nominal) 5k feedback resistor, and the gain trim potentiometer (between Pins 6 and 7) should be increased to 200 Ω. In the bipolar mode, increase the value of the bipolar offset trim potentiometer also to 200 Ω. b.
AD667 The AD667 data and control inputs will float to a Logic 0 if left open. It is recommended that any unused inputs be connected to power ground to improve noise immunity. Fanout for the AD667 is 100 when used with a standard low power Schottky gate output device. 8-BIT MICROPROCESSOR INTERFACE The AD667 interfaces easily to 8-bit microprocessor systems of all types. The control logic makes possible the use of right- or left-justified data formats.
AD667 Right-justified data can be similarly accommodated. The overlapping of data lines is reversed, and the address connections are slightly different. The AD667 still occupies two adjacent locations in the processor’s memory map. In the circuit of Figure 9, location X01 loads the 8 LSBs and location X10 loads the 4 MSBs and updates the output. This configuration uses the first and second rank registers simultaneously. The CS input can be driven from an active-low decoded address.
