Datasheet
AD6645
Rev. D | Page 22 of 24
0.0
74LCX574
CP
D0
D1
D2
D3
D4
D6
D7
GND
O0
O1
O2
O3
O4
O5
O6
O7
VCC
OE
D5
VEE
Q
Q
VCC
D
D
NC
VBB
0.0
VCC
GN D OUT
OE
OE'
GND'
VCC'
OUT'
AIN
C1
C2
D0
D1
D10
D11
D12
D13
D2
D3
D4
D5
D6
D7
D8
D9
DR Y
ENC
VREF
AIN
ENC
GND
GND
GND
DVCC
AVCC
AVCC
GND
GND
AVCC
DVCC
GND
AVC C
GN D
AVC C
GN D
AVC C
GN D
GN D
AVC C
GN D
GN D
AVC C
DVC C
GN D
GND
GND
AVCC
DNC
OVR
DMID
GND
+V
GND
+V
HEADER40
74LCX574
CP
D0
D1
D2
D3
D4
D6
D7
GND
O0
O1
O2
O3
O4
O5
O6
O7
VCC
OE
D5
DO NOT INSTALL
INSTALL JUMPER
OPTIONAL
(SEE NOTE 1)
1. R2 IS INSTALLED FOR INPUT MATCHING ON THE PRIMARY OF T3. R1 5 IS NOT INSTALLED.
R15 IS INSTALLED FOR INPUT MATCHING ON THE SECONDARY OF T3, R2 IS NOT INSTALLED.
3. AC-COUPLED ENCODE IS STANDARD. C5, C6, C33, C34, R1, R11−R14 AND U8 ARE NOT INSTALLED.
NOTES:
2. AC-COUPLED AIN IS STANDARD, R3, R4, R5, R8 AND U3 ARE NOT INSTALLED.
ENC
IF DC-COUPLED AIN IS REQUIRED, C30, R15 AND T3 ARE NOT INSTALLED.
AIN
IF PECL ENCODE IS REQUIRED, CR1 AND T2 ARE NOT INSTALLED.
(SEE NOTE 1)
(SEE NOTE 2)
DC-COUPLED AIN OPTION
80MHz (A D6645)
66.66MHz (A D6644)
AD6644/AD6645
4:1
IMPE DANCE RATIO
4:1
IMPEDANCE RATIO
DO NOT INSTALL
DC-COUPLED ENCODE OPTION (SE E NOTE 3)
OPT_CLK
DO NOT INSTALL
DO NOT INSTALL
J5
J3
J4
R2
60.4
7
021
12
13
14
15
16
17
18
19
10
9
8
6
5
4
3
2
11
U2
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
35 36
37 38
39
4
40
56
78
9
J2
L1
4.7NH
1
10
11
12
13
14
15
16
2
3
4
5
6
7
89
RN4
100
1
10
11
12
13
14
15
16
2
3
4
5
6
7
89
RN3
100
1
10
11
12
13
14
15
16
2
3
4
5
6
7
89
RN2
100
1
10
11
12
13
14
15
16
2
3
4
5
6
7
89
RN1
100
1
2
3
4
5
6
J1
F1
3
16
5
4
T2
ADT4-1WT
+3P3VIN
10U
C31
-5V
+3P3V_XTL
10U
C2
E1
E2
OVR
E6
2
1
5
3
4
NC7SZ32
U6
4
3
5
1
2
U4
NC7SZ32
R10
500
R9
500
C7
0.1U
C8
0.1U
2
3
4
5
6
7
8
9
10
11
12
13
40414244
45464748495052
39
38
37
36
35
34
33
32
31
30
29
28
27
2625
24
232221
20
191817161514
1
51
43U1
0.1U
C32
0.01U
C5
R1
100
0.01U
C6
ENC
ENC
0.1U
C15
0.1U
C22
+5VA
12
F3
+3P3V_XTL
12
F5
14
78
1
3
5
12
10
Y1
+3P3VD
+3P3V
PREF
C1
10U
C38
10U
0.1U
C33
0.1U
C34
F2
R13
66.5
R14
100
+5VA
R12
100
R11
66.5
0.01U
C4 0 C39
0.1U
3
21
CR1
0.1U
C30
C27
0.1U
C29
C 4 0. 1U
C3
0.1U
R8 500
R 5 500
500R3
C26
0.1U
C25
0.1U0. 1U
C24
0.1U
C23
0.01U
C14
0.01U
C13
0.01U
C12
0.01U
C11
0.1U
C10
0.1U
C9
C16
0.1U
C17
0.01U
C18
U10.0U10.0
C21C20
0.01U0.01U
C19
+5VA+5V
+3P3V
12
F4
+3P3VD
+3P3VIN
AIN
R6
25.5
R7
25.5
+5VA
+5VA
+3P3V
+3P3VD
BUFLAT
BUFLAT
3
U3
R4
5
6
7
8
3
2
1
4
U8
MC100LVEL16
R15
178
+5VA
+3P3VD
7
021
12
13
14
15
16
17
18
19
10
9
8
6
5
4
3
2
11
U7
49. 9
R35
OP T_LAT
+3P3V
+3P3V
+5V A
+5V A
+5V A
+5V A
+5V A
+5VA
+5VA
DR _OU T
GN D
VREF-5V
AIN
C28
+5VA
VREF
+3P3V
D
BUFLAT
BUFLAT
DR_OUT
3
16
5
4
T3
ADT4-1WT
B00
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
AD8138ARM
+5VA
4
5
500
6
2
7
VAL
V+
V−
NC
VOCM
8
1
02647-043
Figure 43. Evaluation Board Schematic