AD6644
Rev. D | Page 6 of 24
TIMING DIAGRAM
t
S_DR
t
A
AIN
N
N + 1
N + 2
N + 3
N + 4
t
ENC
t
ENCH
t
ENCL
t
E_FL
t
E_RL
t
E_DR
t
S_E
t
H_E
t
DR
t
H_DR
NN – 1N – 3
D[13:0], OVR
DRY
N + 4N + 3N + 2N + 1N
ENCODE,
ENCODE
N – 2
0971-002
Figure 2. Timing Diagram
