Datasheet

AD6644
Rev. D | Page 4 of 24
DIGITAL SPECIFICATIONS
AV
CC
= 5 V, DV
CC
= 3.3 V; T
MIN
= −25°C, T
MAX
= +85°C, unless otherwise noted.
Table 2.
AD6644AST-40 AD6644AST-65
Parameter Temp Test Level
1
Min Typ Max Min Typ Max
Unit
ENCODE INPUTS (ENCODE,
ENCODE
)
Differential Input Voltage
2
Full IV 0.4 0.4 V p-p
Differential Input Resistance 25°C V 10 10 kΩ
Differential Input Capacitance 25°C V 2.5 2.5 pF
LOGIC OUTPUTS (D13 to D0, DRY, OVR)
Logic Compatibility CMOS CMOS
Logic 1 Voltage
3
Full V 2.5 2.5 V
Logic 0 Voltage
3
Full V 0.4 0.4 V
Output Coding Twos complement Twos complement
DMID Full V DV
CC
/2 DV
CC
/2 V
1
See the Explanation of Test Levels section.
2
All ac specifications tested by driving ENCODE and
ENCODE
differentially. Reference Figure 18 for performance vs. encode power.
3
Digital output logic levels: DV
CC
= 3.3 V, C
LOAD
= 10 pF. Capacitive loads >10 pF degrade performance.
SWITCHING SPECIFICATIONS
AV
CC
= 5 V, DV
CC
= 3.3 V; ENCODE and
ENCODE
= maximum conversion rate MSPS; T
MIN
= –25°C, T
MAX
= +85°C, unless otherwise noted.
Table 3.
AD6644AST-40 AD6644AST-65
Parameter Temp Test Level
1
Min Typ Max Min Typ Max
Unit
Maximum Conversion Rate Full II 40 65 MSPS
Minimum Conversion Rate Full IV 15 15 MSPS
ENCODE Pulse Width High Full IV 10 6.5 ns
ENCODE Pulse Width Low Full IV 10 6.5 ns
1
See the Explanation of Test Levels section.
AV
CC
= 5 V, DV
CC
= 3.3 V; ENCODE and
ENCODE
= maximum conversion rate MSPS; T
MIN
= −25°C, T
MAX
= +85°C, C
LOAD
= 10 Pf,
unless otherwise noted.
Table 4.
AD6644AST-40/65
Parameter Name Temp Test Level
1
Min Typ Max
Unit
ENCODE INPUT PARAMETERS
2
Encode Period @ 65 MSPS t
ENC
Full V 15.4 ns
Encode Period @ 40 MSPS t
ENC
Full V 25 ns
Encode Pulse Width High
3
@ 65 MSPS t
ENCH
Full IV 6.2 7.7 9.2 ns
Encode Pulse Width Low @ 65 MSPS t
ENCL
Full IV 6.2 7.7 9.2 ns
ENCODE/DATA READY
Encode Rising to Data Ready Falling t
DR
Full IV 2.6 3.4 4.6 ns
Encode Rising to Data Ready Rising t
E_DR
t
ENCH
+ t
DR
@ 65 MSPS (50% Duty Cycle) Full IV 10.3 11.1 12.3 ns
@ 40 MSPS (50% Duty Cycle) Full IV 15.1 15.9 17.1 ns
ENCODE/DATA (D13:0), OVR
ENCODE to DATA Falling Low t
E_FL
Full IV 3.8 5.5 9.2 ns
ENCODE to DATA Rising Low t
E_RL
Full IV 3.0 4.3 6.4 ns
ENCODE to DATA Delay (Hold Time)
4
t
H_E
Full IV 3.0 4.3 6.4 ns
ENCODE to DATA Delay (Setup Time)
5
t
S_E
t
ENC
− t
E_FL
Encode = 65 MSPS (50% Duty Cycle) Full IV 6.2 9.8 11.6 ns
Encode = 40 MSPS (50% Duty Cycle) Full IV 15.9 19.4 21.2 ns