Datasheet

AD6620
–9–REV. A
MICROPORT MODE0, READ
Timing is synchronous to CLK; MODE = 0.
t
DD
DATA VALID
t
HC
t
SC
t
HC
t
ZD
t
HA
t
RDY
t
RDY
ADDRESS VALID
t
SAM
t
ZR
N N+1 N+2 N+3 N+4 N
CLK
1
WR
2
RD
2
CS
3
D[7:0]
RDY
1
A[2:0]
NOTES:
1
RDY IS DRIVEN LOW ASYNCHRONOUSLY BY RD AND CS GOING LOW AND RETURNS HIGH ON THE RISING EDGE
OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000), CLK "N+2" OTHERWISE.
2
THE SIGNAL, WR, MAY REMAIN HIGH AND RD MAY REMAIN LOW TO CONTINUE READ MODE.
3
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE READ.
Figure 17. MODE0 Read Timing Requirements and Switching Characteristics
MICROPORT MODE0, WRITE
Timing is synchronous to CLK; MODE = 0.
DATA VALID
t
HC
t
SC
t
HC
t
SC
t
HM
ADDRESS VALID
N N+1 N+2 N+3 N*
CLK
1
WR
2
RD
2
CS
3
D[7:0]
RDY
A[2:0]
NOTES:
1
RDY IS DRIVEN LOW ASYNCHRONOUSLY BY WR AND CS GOING LOW AND RETURNS HIGH ON THE
RISING EDGE OF CLK "N+2".
2
THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.
3
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE.
* THE NEXT WRITE MAY BE INITIATED ON CLK, N*.
t
HA
t
RDY
t
RDY
t
SAM
t
SAM
Figure 18. MODE0 Write Timing Requirements and Switching Characteristics