Datasheet

AD6620
–7–REV. A
TIMING DIAGRAMS
CLK, INPUTS, PARALLEL OUTPUTS
RESET with PAR/SER = “1” establishes Parallel Outputs active.
t
CLKH
t
CLKL
t
CLK
CLK
Figure 3. CLK Timing Requirements
CLK
IN[15:0]
EXP[2:0]
A/B
t
SI
t
HI
DATA
Figure 4. Input Data Timing Requirements
CLK
OUT[15:0]
VALID OUTPUT DATA
DV
OUT
I/Q
OUT
t
DPR
t
DPF
I
Q
I
Q
I
A
Q
A
I
B
Q
B
t
DPF
Figure 5. Parallel Output Switching Characteristics
SYNC PULSES: SLAVE OR MASTER
t
SY
t
HY
CLK
SYNC
NCO
SYNC
CIC
SYNC
RCF
NOTE:
IN THE SLAVE MODE WITH SINGLE CHANNEL OPERATION, THE WIDTH
OF THE SYNC_NCO SHOULD BE ONE SAMPLE CLOCK CYCLE. IN DUAL
CHANNEL MODE, THE PULSEWIDTH SHOULD BE TWO SAMPLE CLOCK
CYCLES. IF A PULSE LONGER THAN SPECIFIED IS USED, THE NCO WILL
BE INHIBITED AND NOT INCREMENT PROPERLY.
Figure 6. SYNC Slave Timing Requirements
CLK
t
CHP
t
CPL
t
CS
t
CH
IN[15:0]
E[2:0]
A/B
N+1
N
t
CLK
Figure 7. SYNC Master Delay
t
RESL
RESET
Figure 8. Reset Timing Requirements