Datasheet

AD6620
–34–
REV. A
DATA VALID
t
SC
ADDRESS VALID
N
N+1 N+2
N+3
CLK
1
R/W
2
DS
2
CS
3
D[7:0]
DTACK
A[2:0]
t
SAM
N+4
N
t
HC
t
DD
t
HC
t
ZD
t
HA
t
DTACK
t
DTACK
NOTES:
1
DTACK IS DRIVEN LOW ON THE RISING EDGE OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000),
CLK "N=2" OTHERWISE.
2
THE SIGNAL, R/W MAY REMAIN HIGH AND DS MAY REMAIN LOW TO CONTINUE READ MODE.
3
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE ACCESS
AND FORCE DTACK HIGH.
t
SC
t
ZR
Figure 45. Mode 1 Read (MODE = VDD)
Mode = 1
If the MODE input is held high the interface is in Mode 1. In
Mode 1 the RD signal becomes the data strobe (DS) and the
WR signal becomes a read/write (R/W) select signal. In this
t
SC
N
N+1 N+2
N+3
t
SAM
N*
t
DTACK
t
SC
CLK
1
R/W
2
DS
2
CS
3
D[7:0]
DTACK
A[2:0]
t
HC
t
HC
t
DTACK
t
SAM
t
HM
t
HA
NOTES:
1
ON RISING EDGE OF "N+3" CLK, DTACK IS DRIVEN LOW.
2
THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.
3
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE
AND FORCE DTACK HIGH.
*THE NEXT WRITE MAY BE INITIATED ON CLK
,
N*
DATA VALID
ADDRESS VALID
Figure 46. Mode 1 Write (MODE = VDD)
mode the DTACK signal goes low when data is available during
a read or when data has been latched during a write. The DTACK
signal stays low until the DS signal is released.