Datasheet

AD6620
–33–REV. A
Mode = 0
If MODE is low during the access, the interface is in Mode 0.
In Mode 0 the CS, RD and the WR lines control the access
type. While an access is being performed, or if the serial port
DATA VALID
t
HC
t
SC
t
HC
t
SC
t
HM
ADDRESS VALID
N N+1 N+2 N+3 N*
CLK
1
WR
2
RD
2
CS
3
D[7:0]
RDY
A[2:0]
NOTES:
1
RDY IS DRIVEN LOW ASYNCHRONOUSLY BY WR AND CS GOING LOW AND RETURNS HIGH ON THE
2
THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.
3
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE.
*THE NEXT WRITE MAY BE INITIATED ON CLK, N.
t
HA
t
RDYHt
RDYL
t
SAM
t
SAM
RISING EDGE OF CLK "N+2".
Figure 44. Mode 0 Write (MODE = GND)
is accessing the chip, the RDY line goes low at the start of
the access. When the internal cycle is complete the RDY line
is released.
t
DD
DATA VALID
t
HC
t
SC
t
HC
t
ZD
t
HA
t
RDY
t
RDY
ADDRESS VALID
t
SAM
t
ZR
N N+1 N+2 N+3 N+4 N
CLK
1
WR
2
RD
2
CS
3
D[7:0]
RDY
1
A[2:0]
NOTES:
1
RDY IS DRIVEN LOW ASYNCHRONOUSLY BY RD AND CS GOING LOW AND RETURNS HIGH ON THE RISING EDGE
OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000), CLK "N+2" OTHERWISE.
2
THE SIGNAL, WR, MAY REMAIN HIGH AND RD MAY REMAIN LOW TO CONTINUE READ MODE.
3
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE READ.
Figure 43. Mode 0 Read (MODE = GND)