Datasheet

AD6620
–10–
REV. A
MICROPORT MODE1, READ
Timing is synchronous to CLK; MODE = 1.
DATA VALID
t
SC
ADDRESS VALID
N
N+1 N+2
N+3
CLK
1
R/W
2
DS
2
CS
3
D[7:0]
DTACK
A[2:0]
t
SAM
N+4
N
t
HC
t
DD
t
HC
t
ZD
t
HA
t
DTACK
t
DTACK
NOTES:
1
DTACK IS DRIVEN LOW ON THE RISING EDGE OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000),
CLK "N=2" OTHERWISE.
2
THE SIGNAL, R/W MAY REMAIN HIGH AND DS MAY REMAIN LOW TO CONTINUE READ MODE.
3
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE ACCESS
AND FORCE DTACK HIGH.
t
SC
t
ZR
Figure 19. MODE1 Read Timing Requirements and Switching Characteristics
MICROPORT MODE1, WRITE
Timing is synchronous to CLK; MODE = 1.
t
SC
N
N+1 N+2
N+3
t
SAM
N*
t
DTACK
t
SC
CLK
1
R/W
2
DS
2
CS
3
D[7:0]
DTACK
A[2:0]
t
HC
t
HC
t
DTACK
t
SAM
t
HM
t
HA
NOTES:
1
ON RISING EDGE OF "N+3" CLK, DTACK IS DRIVEN LOW.
2
THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.
3
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE
AND FORCE DTACK HIGH.
* THE NEXT WRITE MAY BE INITIATED ON CLK, N*.
DATA VALID
ADDRESS VALID
Figure 20. MODE1 Write Timing Requirements and Switching Characteristics