Datasheet

AD654

REV. A

–8–

C900c–10–6/88

PRINTED IN U.S.A.

Figure 13 illustrates this with a circuit offering 2 MHz full scale.

In this circuit the AD654 is operated at a full scale (FS) of

1 mA, with a C

of 100 pF. This achieves a basic device FS fre-

quency of 1 MHz across C

. The P channel JFETs, Q1 and

Q2, buffer the differential timing capacitor waveforms to a low

impedance level where the push-pull signal is then ac coupled to

the high speed comparator A2. Hysteresis is used, via R7, for

non-ambiguous switching and to eliminate the oscillations which

would otherwise occur at low frequencies.

The net result of this is a very high speed circuit which does not

compromise the AD654 dynamic range. This is a result of the

FET buffers typically having only a few pA of bias current. The

high end dynamic range is limited, however, by parasitic package

and layout capacitances in shunt with C

, as well as those from

each node to ac ground. Minimizing the lead length between

A2–6/A2–7 and Q1/Q2 in PC layout will help. A ground plane

Figure 13. 2 MHz, Frequency Doubling V/F

will also help stability. Figure 14 shows the waveforms V1–V4

found at the respective points shown in Figure 13.

The output of the comparator is a complementary square wave

at 1 MHz FS. Unlike pulse train output V/F converters, each

half-cycle of the AD654 output conveys information about the

input. Thus it is possible to count edges, rather than full cycles

of the output, and double the effective output frequency. The

XOR gate following A2 acts as an edge detector producing a

short pulse for each input state transition. This effectively

doubles the V/F FS frequency to 2 MHz. The final result is a

1 V full-scale input V/F with a 2 MHz full-scale output capabil-

ity; typical nonlinearity is 0.5%.

Figure 14. Waveforms of 2 MHz Frequency Doubler

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Pin Plastic DIP

8-Pin SOIC