Datasheet

Data Sheet AD650
Rev. E | Page 9 of 20
If the approximate amount of noise that appears on C
INT
is known
(V
NOISE
), then the value of C
INT
can be checked using the following
inequality:
NOISES
OS
INT
VV
At
C




V3
101
3
(8)
For example, consider an application calling for a maximum
frequency of 75 kHz, a 0 V to 1 V signal range, and supply
voltages of only ±9 V. The component selection guide of Figure 9
is used to select 2.0 kΩ for R
IN
and 1000 pF for C
OS
. This results
in a one-shot time period of approximately 7 μs. Substituting
75 kHz into Equation 7 yields a value of 1300 pF for C
INT
. When
the input signal is near zero, 1 mA flows through the integration
capacitor to the switched current sink during the reset phase,
causing the voltage across C
INT
to increase by approximately 5.5 V.
Because the integrator output stage requires approximately 3 V
headroom for proper operation, only 0.5 V margin remains for
integrating extraneous noise on the signal line. A negative noise
pulse at this time could saturate the integrator, causing an error
in signal integration. Increasing C
INT
to 1500 pF or 2000 pF
provides much more noise margin, thereby eliminating this
potential trouble spot.
1MHz
100kHz
10kHz
50 100 1000
FREQUENCY FULL-SCALE
C
OS
(pF)
00797-008
INPUT
RESISTOR
16.9k
20k
40.2k
100k
Figure 9. Full-Scale Frequency vs. C
OS
100
20
50 100 1000
TYPICAL NONLINEARITY (ppm)
ONE SHOT CAPACITOR
C
OS
(pF)
1000
INPUT
RESISTOR
16.9k
40.2k
100k
20k
00797-009
Figure 10. Typical Nonlinearity vs. C
OS