Datasheet

REV. E
AD633
–4–
FUNCTIONAL DESCRIPTION
The AD633 is a low cost multiplier comprising a translinear
core, a buried Zener reference, and a unity gain connected
output amplifier with an accessible summing node. Figure 1
shows the functional block diagram. The differential X and Y
inputs are converted to differential currents by voltage-to-current
converters. The product of these currents is generated by the
multiplying core. A buried Zener reference provides an overall
scale factor of 10 V. The sum of (X × Y)/10 + Z is then applied
to the output amplifier. The amplifier summing node Z allows
the user to add two or more multiplier outputs, convert the
output voltage to a current, and configure various analog com-
putational functions.
AD633
1
2
3
4
8
7
6
5
1
10V
X1
X2
Y1
Y2
W
Z
+V
S
–V
S
A
1
1
Figure 1. Functional Block Diagram (AD633JN
Pinout Shown)
Inspection of the block diagram shows the overall transfer func-
tion to be:
W
XXYY
V
Z=
−
( )
−
( )
+
1212
10
(1)
ERROR SOURCES
Multiplier errors consist primarily of input and output offsets,
scale factor error, and nonlinearity in the multiplying core. The
input and output offsets can be eliminated by using the optional
trim of Figure 2. This scheme reduces the net error to scale factor
errors (gain error) and an irreducible nonlinearity component in
the multiplying core. The X and Y nonlinearities are typically
0.4% and 0.1% of full scale, respectively. Scale factor error is
typically 0.25% of full scale. The high impedance Z input should
always be referenced to the ground point of the driven system,
particularly if this is remote. Likewise, the differential X and Y
inputs should be referenced to their respective grounds to realize
the full accuracy of the AD633.
1k⍀
300k⍀
50k⍀
+V
S
–V
S
ⴞ50mV
TO APPROPRIATE
INPUT TERMINAL
(e.g., X
2
, X
2
, Z)
Figure 2. Optional Offset Trim Configuration
APPLICATIONS
The AD633 is well suited for such applications as modulation
and demodulation, automatic gain control, power measurement,
voltage controlled amplifiers, and frequency doublers. Note that
these applications show the pin connections for the AD633JN
pinout (8-lead DIP), which differs from the AD633JR pinout
(8-lead SOIC).
Multiplier Connections
Figure 3 shows the basic connections for multiplication. The X
and Y inputs will normally have their negative nodes grounded,
but they are fully differential, and in many applications the
grounded inputs may be reversed (to facilitate interfacing with
signals of a particular polarity while achieving some desired
output polarity) or both may be driven.
W =
(X
1
– X
2
) (Y
1
– Y
2
)
+ Z
10V
X
INPUT
OPTIONAL SUMMING
INPUT, Z
0.1␮F
+15V
–15V
8
7
6
5
1
2
3
4
AD633JN
0.1␮F
X1
X2
Y1
Y2
–V
S
+V
S
W
Z
Y
INPUT
Figure 3. Basic Multiplier Connections
Squaring and Frequency Doubling
As Figure 4 shows, squaring of an input signal, E, is achieved
simply by connecting the X and Y inputs in parallel to produce
an output of E
2
/10 V. The input may have either polarity, but
the output will be positive. However, the output polarity may be
reversed by interchanging the X or Y inputs. The Z input may
be used to add a further signal to the output.
0.1␮F
+15V
E
W =
E
2
10V
8
7
6
5
1
2
3
4
AD633JN
0.1␮F
X1
X2
Y1
Y2
–V
S
+V
S
W
Z
–15V
Figure 4. Connections for Squaring
When the input is a sine wave E sin ωt, this squarer behaves as a
frequency doubler, since
Et
V
E
V
t
sin
cos
ω
ω
()
=−
()
2
2
10 20
12
(2)
Equation 2 shows a dc term at the output that will vary strongly
with the amplitude of the input, E. This can be avoided using
the connections shown in Figure 5, where an RC network is
used to generate two signals whose product has no dc term. It
uses the identity:
cos sin sinθθ θ=
()
1
2
2
(3)