Datasheet

AD628
Rev. G | Page 16 of 20
APPLICATIONS INFORMATION
GAIN ADJUSTMENT
The AD628 system gain is provided by an architecture
consisting of two amplifiers (see
Figure 29). The gain of the
input stage is fixed at 0.1; the output buffer is user adjustable
as G
A2
= 1 + R
EXT1
/R
EXT2
. The system gain is then
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+×=
EXT2
EXT1
TOTAL
R
R
G 10.1
(1)
At a 2 nA maximum, the input bias current of the buffer amplifier
is very low and any offset voltage induced at the buffer amplifier
by its bias current may be neglected (2 nA × 10 kΩ = 20 µV).
However, to absolutely minimize bias current effects, select
R
EXT1
and R
EXT2
so that their parallel combination is 10 kΩ. If
practical resistor values force the parallel combination of R
EXT1
and R
EXT2
below 10 kΩ, add a series resistor (R
EXT3
) to make up
for the difference.
Table 5 lists several values of gain and
corresponding resistor values.
Table 5. Nearest Standard 1% Resistor Values for
Various Gains (see
Figure 29)
Total Gain
(V/V)
A2 Gain
(V/V)
R
EXT1
(Ω) R
EXT2
(Ω) R
EXT3
(Ω)
0.1 1 10 k ∞ 0
0.2 2 20 k 20 k 0
0.25 2.5 25.9 k 18.7 k 0
0.5 5 49.9 k 12.4 k 0
1 10 100 k 11 k 0
2 20 200 k 10.5 k 0
5 50 499 k 10.2 k 0
10 100 1 M 10.2 k 0
To set the system gain to <0.1, create an attenuator by placing
Resistor R
EXT4
from Pin 4 (C
FILT
) to the reference voltage. A
divider is formed by the 10 kΩ resistor that is in series with the
positive input of A2 and Resistor R
EXT4
. A2 is configured for
unity gain.
Using a divider and setting A2 to unity gain yields
1
k10
0.1
/
×
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
×=
EXT4
EXT4
DIVIDERW
R
R
G
INPUT VOLTAGE RANGE
VREF and the supply voltage determine the common-mode
input voltage range. The relation is expressed by
REF
SCM
VVV
UPPER
10)V2.1–(11 −
≤
+
(2)
REF
SCM
VV 10)V2.1(11V
LOWER
−
+
≥
−
where:
V
S+
is the positive supply.
V
S−
is the negative supply.
1.2 V is the headroom needed for suitable performance.
Equation 2 provides a general formula for calculating the
common-mode input voltage range. However, keep the AD628
within the maximum limits listed in
Tabl e 1 to maintain
optimal performance. This is illustrated in
Figure 30 where the
maximum common-mode input voltage is limited to ±120 V.
Figure 31 shows the common-mode input voltage bounds for
single-supply voltages.
–200
–150
–100
–50
0
50
INPUT COMMON-MODE VOLTAGE (V)
100
150
200
862401012
SUPPLY VOLTAGE (±V)
02992-035
1416
MAXIMUM INPUT COMMON-MODE
VOLTAGE WHEN V
REF
= GND
Figure 30. Input Common-Mode Voltage vs. Supply Voltage
for Dual Supplies
–80
–60
–40
–20
0
20
40
60
80
100
INPUT COMMON-MODE VOLTAGE (V)
862401012
SINGLE-SUPPLY VOLTAGE (V)
02992-034
1416
MAXIMUM INPUT COMMON-MODE
VOLTAGE WHEN V
REF
= MIDSUPPLY
Figure 31. Input Common-Mode Voltage vs.
Supply Voltage for Single Supplies