Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Table of Contents
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Typical Performance Characteristics
- Theory of Operation
- Using the AD627
- Basic Connections
- Setting the Gain
- Reference Terminal
- Input Range Limitations in Single-Supply Applications
- Output Buffering
- Input and Output Offset Errors
- Make vs. Buy: A Typical Application Error Budget
- Errors Due to AC CMRR
- Ground Returns for Input Bias Currents
- Layout and Grounding
- Input Protection
- RF Interference
- Applications Circuits
- Outline Dimensions

Data Sheet AD627
Rev. E | Page 11 of 24
GAIN (V/V)
10
0.1
5 1k
SETTLING TIME (ms)
1
100
10
00782-015
Figure 17. Settling Time to 0.01% vs. Gain for a 5 V Step at Output, R
L
= 20 kΩ,
C
L
= 100 pF, V
S
= ±5 V
1V1mV 50µs
00782-016
Figure 18. Large Signal Pulse Response and Settling Time, G = –5, R
L
= 20 kΩ,
C
L
= 100 pF (1.5 mV = 0.01%)
1V1mV 50µs
00782-017
Figure 19. Large Signal Pulse Response and Settling Time, G = −10,
R
L
= 20 kΩ, C
L
= 100 pF (1.0 mV = 0.01%)
OUTPUT PULSE (V)
400
200
0
0
±10
SETTLING TIME (µs)
±2 ±4
±6 ±8
300
100
00782-018
Figure 20. Settling Time to 0.01% vs. Output Swing, G = +5, R
L
= 20 kΩ,
C
L
= 100 pF
200µV
1V 100µs
00782-019
Figure 21. Large Signal Pulse Response and Settling Time, G = –100,
R
L
= 20 kΩ, C
L
= 100 pF (100 µV = 0.01%)
200µV
1V 500µs
00782-020
Figure 22. Large Signal Pulse Response and Settling Time, G = –1000,
R
L
= 20 kΩ, C
L
= 100 pF (10 µV = 0.01%)