Datasheet

REV. C
AD624
–12–
225.3⍀
124⍀
4445.7⍀
80.2⍀
50⍀
V
B
50⍀
20k⍀ 10k⍀
10k⍀
10k⍀
AD624
G = 100
G = 200
G = 500
RG
1
RG
2
–INPUT
(+INPUT)
V
OUT
20k⍀
10k⍀
+INPUT
(–INPUT)
AD7528
1/2
AD712
256:1
DATA
INPUTS
CS
WR
DAC A/DAC B
DB0
DB7
+V
S
DAC A
DAC B
1/2
AD712
Figure 40. Programmable Output Gain Using a DAC
AUTOZERO CIRCUITS
In many applications it is necessary to provide very accurate
data in high gain configurations. At room temperature the offset
effects can be nulled by the use of offset trimpots. Over the
operating temperature range, however, offset nulling becomes a
problem. The circuit of Figure 41 shows a CMOS DAC operat-
ing in the bipolar mode and connected to the reference terminal
to provide software controllable offset adjustments.
AD624
–V
S
+V
S
V
OUT
G = 100
G = 200
G = 500
RG
1
RG
2
+INPUT
–INPUT
DATA
INPUTS
CS
WR
MSB
LSB
+V
S
AD7524
C1
OUT1
OUT2
1/2
AD712
R
FB
+V
S
R3
20k⍀
R4
10k⍀
R5
20k⍀
–V
S
R6
5k⍀
–V
S
GND
AD589
39k⍀ V
REF
1/2
AD712
Figure 41. Software Controllable Offset
In many applications complex software algorithms for autozero
applications are not available. For these applications Figure 42
provides a hardware solution.
AD624
–V
S
+V
S
V
OUT
RG
1
RG
2
1k⍀
12 11
910
0.1␮F LOW
LEAKAGE
CH
15 16
14
13
V
SS
V
DD
GND
A1 A2 A3 A4
AD7510DIKD
200␮s
ZERO PULSE
AD542
Figure 42. Autozero Circuit
The microprocessor controlled data acquisition system shown in
Figure 43 includes includes both autozero and autogain capabil-
ity. By dedicating two of the differential inputs, one to ground
and one to the A/D reference, the proper program calibration
cycles can eliminate both initial accuracy errors and accuracy
errors over temperature. The autozero cycle, in this application,
converts a number that appears to be ground and then writes
that same number (8 bit) to the AD624 which eliminates the
zero error since its output has an inverted scale. The autogain
cycle converts the A/D reference and compares it with full scale.
A multiplicative correction factor is then computed and applied
to subsequent readings.
RG
1
RG
2
AD624
1/2
AD712
AD583
AGND
V
IN
V
REF
AD574A
AD7507
EN A1
A2
A0
ADDRESS BUS
–V
REF
5k⍀
10k⍀
20k⍀
LATCH
20k⍀
1/2
AD712
CONTROL
DECODE
AD7524
MICRO-
PROCESSOR
Figure 43. Microprocessor Controlled Data Acquisition
System