Datasheet

AD598
REV. A
–7–
8. C2, C3 and C4 are a function of the desired bandwidth of
the AD598 position measurement subsystem. They should
be nominally equal values.
C2 = C3 = C4 = 10
–4
Farad Hz/f
SUBSYSTEM
(Hz)
If the desired system bandwidth is 250 Hz, then
C2 = C3 = C4 = 10
–4
Farad Hz/250 Hz = 0.4 µ F
See Figures 13, 14 and 15 for more information about
AD598 bandwidth and phase characterization.
9. In order to Compute R2, which sets the AD598 gain or full-
scale output range, several pieces of information are needed:
a. LVDT sensitivity, S
b. Full-scale core displacement, d
c. Ratio of manufacturer recommended primary drive level,
V
PRI
to (V
A
+ V
B
) computed in Step 4.
LVDT sensitivity is listed in the LVDT manufacturer’s cata-
log and has units of millivolts output per volts input per inch
displacement. The E100 has a sensitivity of 2.4 mV/V/mil.
In the event that LVDT sensitivity is not given by the manu-
facturer, it can be computed. See section on Determining
LVDT Sensitivity.
For a full-scale displacement of d inches, voltage out of the
AD598 is computed as
V
OUT
= S ×
V
PRI
(V
A
+V
B
)






× 500 µA × R2 × d.
V
OUT
is measured with respect to the signal reference,
Pin 17 shown in Figure 7.
Solving for R2,
R2 =
V
OUT
×(V
A
+V
B
)
S ×V
PRI
× 500 µA × d
(1)
Note that V
PRI
is the same signal level used in Step 4 to
determine (V
A
+ V
B
).
For V
OUT
= 20 V full-scale range (±10 V) and d = 0.2 inch
full-scale displacement (±0.1 inch),
R2 =
20V × 2. 70 V
2. 4 × 3 × 500 µA × 0.2
= 75. 3 kΩ
V
OUT
as a function of displacement for the above example is
shown in Figure 9.
+
10
+
0.1 d0.1
–
10
–
V
OUT
( VOLTS)
(INCHES)
Figure 9. V
OUT
( ± 10 V Full Scale)
vs. Core Displacement (
± 0.1 Inch)
10. Selections of R3 and R4 permit a positive or negative output
voltage offset adjustment.
V
OS
= 1. 2 V × R 2 ×
1
R 3 + 5 k Ω *
–
1
R 4 + 5 k Ω *






(2)
*These values have a ±20% tolerance.
For no offset adjustment R3 and R4 should be open circuit.
To design a circuit producing a 0 V to +10 V output for a
displacement of ±0.1 inch, set V
OUT
to +10 V, d = 0.2 inch
and solve Equation (1) for R2.
R2 = 37.6 k
Ω
This will produce a response shown in Figure 10.
+
5
+
0.1 d0.1
–
5
–
(INCHES)
V
OUT
( VOLTS)
Figure 10. V
OUT
( ± 5 V Full Scale)
vs. Core Displacement (
± 0.1 Inch)
In Equation (2) set V
OS
= 5 V and solve for R3 and R4.
Since a positive offset is desired, let R4 be open circuit.
Rearranging Equation (2) and solving for R3
R3 =
1. 2 × R 2
V
OS
–5kΩ=4.02 kΩ
Figure 11 shows the desired response.
+
10
0.1
–
+
0.1 d
+
5
(INCHES)
V
OUT
( VOLTS)
Figure 11. V
OUT
(0 V–10 V Full Scale)
vs. Displacement (
± 0.1 Inch)
DESIGN PROCEDURE
SINGLE SUPPLY OPERATION
Figure 12 shows the single supply connection method.
For single supply operation, repeat Steps 1 through 10 of the
design procedure for dual supply operation, then complete the
additional Steps 11 through 14 below. R5, R6 and C5 are addi-
tional component values to be determined. V
OUT
is measured
with respect to SIGNAL REFERENCE.
11. Compute a maximum value of R5 and R6 based upon the
relationship
R5 + R6 ≤ V
PS
/100 µA
12. The voltage drop across R5 must be greater than
2 + 10 kΩ*
1. 2 V
R 4 + 5 k Ω
+ 250 µA +
V
OUT
4 × R2






Volts
Therefore
R5≥
2+10 kΩ*
1. 2 V
R4+5kΩ
+250 µA +
V
OUT
4 ×R2






100 µA
Ohms
*These values have ±20% tolerance.
Based upon the constraints of R5 + R6 (Step 11) and R5
(Step 12), select an interim value of R6.