Datasheet

Data Sheet AD5933
Rev. E | Page 5 of 40
Parameter
Y Version
1
Unit Test Conditions/Comments
Min Typ Max
RECEIVE STAGE
Input Leakage Current 1 nA To VIN pin
Input Capacitance
6
0.01 pF Pin capacitance between VIN and GND
Feedback Capacitance (C
FB
) 3 pF Feedback capacitance around current-
to-voltage amplifier; appears in
parallel with feedback resistor
ANALOG-TO-DIGITAL CONVERTER
6
Resolution 12 Bits
Sampling Rate 1 MSPS ADC throughput rate
TEMPERATURE SENSOR
Accuracy ±2.0 °C −40°C to +125°C temperature range
Resolution 0.03 °C
Temperature Conversion Time 800 μs Conversion time of single temperature
measurement
LOGIC INPUTS
Input High Voltage (V
IH
) 0.7 × VDD
Input Low Voltage (V
IL
) 0.3 × VDD
Input Current
7
1 µA T
A
= 25°C
Input Capacitance 7 pF T
A
= 25°C
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD (Normal Mode ) 10 15 mA VDD = 3.3 V
17 25 mA VDD = 5.5 V
IDD (Standby Mode) 11 mA VDD = 3.3 V; see the Control Register
(Register Address 0X80, Register
Address 0X81) section
16 mA VDD = 5.5 V
IDD (Power-Down Mode) 0.7 5 µA VDD = 3.3 V
1 8 µA VDD = 5.5 V
1
Temperature range for Y version = −40°C to +125°C, typical at 25°C.
2
The lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the AD5933.
3
Refer to Figure 14, Figure 15, and Figure 16 for the internal oscillator frequency distribution with temperature.
4
The peak-to-peak value of the ac output excitation voltage scales with supply voltage according to the following formula:
Output Excitation Voltage (V p-p) = [2/3.3] × VDD
where VDD is the supply voltage.
5
The dc bias value of the output excitation voltage scales with supply voltage according to the following formula:
Output Excitation Bias Voltage (V) = [2/3.3] × VDD
where VDD is the supply voltage.
6
Guaranteed by design or characterization, not production tested. Input capacitance at the VOUT pin is equal to pin capacitance divided by open-loop gain of current-
to-voltage amplifier.
7
The accumulation of the currents into Pin 8, Pin 15, and Pin 16.