Datasheet

Data Sheet AD5933
Rev. E | Page 25 of 40
FREQUENCY INCREMENT REGISTER (REGISTER
ADDRESS 0x85, REGISTER ADDRESS 0x86,
REGISTER ADDRESS 0x87)
The default value upon reset is as follows: D23 to D0 are not reset
on power-up. After a reset command, the contents of this register
are not reset.
The frequency increment register contains a 24-bit represen-
tation of the frequency increment between consecutive frequency
points along the sweep. For example, if the user requires an
increment step of 10 Hz using a 16.0 MHz clock, the user
should program the value of 0x00 to Register Address 0x85, the
value of 0x01 to Register Address 0x86m, and the value of 0x4F
to Register Address 0x87.
The formula for calculating the increment frequency is given by
F00014x02
4
MHz16
Hz10
27
≡×




















=CodeIncrementFrequency
The user programs the value 0x00 to Register Address 0x85, the
value 0x01 to Register Address 0x86, and the value 0x4F to
Register Address 0x87.
NUMBER OF INCREMENTS REGISTER (REGISTER
ADDRESS 0x88, REGISTER ADDRESS 0x89)
The default value upon reset is as follows: D8 to D0 are not reset
on power-up. After a reset command, the contents of this
register are not reset.
Table 12. Number of Increments Register
Reg Bits Description Function Format
0x88 D15 to D9 Don’t care Read or
write
Integer number
stored in binary
format
D8 Number of
increments
Read or
write
0x89
D8 to D0
Number of
increments
Read or
write
Integer number
stored in binary
format
This register determines the number of frequency points in the
frequency sweep. The number of points is represented by a 9-bit
word, D8 to D0. D15 to D9 are don’t care bits. This register, in
conjunction with the start frequency register and the increment
frequency register, determines the frequency sweep range for
the sweep operation. The maximum number of increments that
can be programmed is 511.
NUMBER OF SETTLING TIME CYCLES
REGISTER (REGISTER ADDRESS 0x8A,
REGISTER ADDRESS 0x8B)
The default value upon reset is as follows: D10 to D0 are not
reset on power-up. After a reset command, the contents of this
register are not reset (see Table 13).
This register determines the number of output excitation cycles
that are allowed to pass through the unknown impedance, after
receipt of a start frequency sweep, increment frequency, or
repeat frequency command, before the ADC is triggered to
perform a conversion of the response signal. The number of
settling time cycles register value determines the delay between
a start frequency sweep/increment frequency /repeat frequency
command and the time an ADC conversion commences. The
number of cycles is represented by a 9-bit word, D8 to D0. The
value programmed into the number of settling time cycles
register can be increased by a factor of 2 or 4 depending upon
the status of bits D10 to D9. The five most significant bits, D15
to D11, are don’t care bits. The maximum number of output
cycles that can be programmed is 511 × 4 = 2044 cycles. For
example, consider an excitation signal of 30 kHz. The
maximum delay between the programming of this frequency
and the time that this signal is first sampled by the ADC is ≈
511 × 4 × 33.33 µs = 68.126 ms. The ADC takes 1024 samples,
and the result is stored as real data and imaginary data in
Register Address 0x94 to Register Address 0x97. The conversion
process takes approximately 1 ms using a 16.777 MHz clock.
Table 13. Number of Settling Times Cycles Register
Register Bits Description Function Format
0x8A D15 to D11 Don’t care Read or write Integer number stored in
binary format
D10 to D9 2-bit decode
D10 D9 Description
0 0 Default
0 1 No. of cycles × 2
1 0 Reserved
1 1 No. of cycles × 4
D8 MSB number of settling time cycles
0x8B D7 to D0 Number of settling time cycles Read or write