Datasheet

AD5932 Data Sheet
Rev. A | Page 6 of 28
TIMING SPECIFICATIONS
All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and are timed from a voltage level of (V
IL
+ V
IH
)/2 (see Figure 3 to
Figure 6). DVDD = 2.3 V to 5.5 V; AGND = DGND = 0 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
Limit at T
MIN
, T
MAX
Unit Conditions/Comments
t
1
20 ns min MCLK period
t
2
8 ns min MCLK high duration
t
3
8 ns min MCLK low duration
t
4
25 ns min SCLK period
t
5
10 ns min SCLK high time
t
6
10 ns min SCLK low time
t
7
5 ns min FSYNC to SCLK falling edge setup time
t
8
10 ns min FSYNC to SCLK hold time
t
9
5 ns min Data setup time
t
10
3 ns min Data hold time
t
11
2 × t
1
ns min Minimum CTRL pulse width
t
12
0 ns min CTRL rising edge to MCLK falling edge setup time
t
13
10 × t
1
ns typ CTRL rising edge to VOUT delay (initial pulse, includes initialization)
8 × t
1
ns typ CTRL rising edge to VOUT delay (initial pulse, includes initialization)
t
14
1 × t
1
ns typ Frequency change to SYNC output, each frequency increment
t
15
2 × t
1
ns typ Frequency change to SYNC output, end of scan
t
16
20 ns max MCLK falling edge to MSBOUT
1
Guaranteed by design, not production tested.
MASTER CLOCK AND TIMING DIAGRAMS
MCLK
t
3
t
2
t
1
05416-003
Figure 3. Master Clock
SCLK
FSYNC
SDATA
D15 D14 D2 D1 D0 D15 D14
t
7
t
9
t
6
t
8
t
10
t
5
t
4
05416-004
Figure 4. Serial Timing