Datasheet

AD585–SPECIFICATIONS
Model AD585J AD585A AD585S
Min Typ Max Min Typ Max Min Typ Max Units
SAMPLE/HOLD CHARACTERISTICS
Acquisition Time, 10 V Step to 0.01% 333µs
20 V Step to 0.01% 5 5 5 µs
Aperture Time, 20 V p-p Input,
HOLD 0 V 353535ns
Aperture Jitter, 20 V p-p Input,
HOLD 0 V 0.5 0.5 0.5 ns
Settling Time, 20 V p-p Input,
HOLD 0 V, to 0.01% 0.5 0.5 0.5 µs
Droop Rate 111mV/ms
Droop Rate T
MIN
to T
MAX
Doubles Every 10°C Double Every 10°C Doubles Every 10°C
Charge Transfer 0.3 0.3 0.3 pC
Sample-to-Hold Offset –3 3 –3 3 –3 3 mV
Feedthrough
20 V p-p, 10 kHz Input 0.5 0.5 0.5 mV
TRANSFER CHARACTERISTICS
1
Open Loop Gain
V
OUT
= 20 V p-p, R
L
= 2k 200,000 200,000 200,000 V/V
Application Resistor Mismatch 0.3 0.3 0.3 %
Common-Mode Rejection
V
CM
= ±10 V 80 80 80 dB
Small Signal Gain Bandwidth
V
OUT
= 100 mV p-p 2.0 2.0 2.0 MHz
Full Power Bandwidth
V
OUT
= 20 V p-p 160 160 160 kHz
Slew Rate
V
OUT
= 20 V p-p 10 10 10 V/µs
Output Resistance (Sample Mode)
I
OUT
= ±10 mA 0.05 0.05 0.05 Ω
Output Short Circuit Current 50 50 50 mA
Output Short Circuit Duration Indefinite Indefinite Indefinite
ANALOG INPUT CHARACTERISTICS
Offset Voltage 522mV
Offset Voltage, T
MIN
to T
MAX
633mV
Bias Current 222nA
Bias Current, T
MIN
to T
MAX
552050
2
nA
Input Capacitance, f = 1 MHz 10 10 10 pF
Input Resistance, Sample or Hold
20 V p-p Input, A = +1 10
12
10
12
10
12
Ω
DIGITAL INPUT CHARACTERISTICS
TTL Reference Output 1.2 1.4 1.6 1.2 1.4 1.6 1.2 1.4 1.6 V
Logic Input High Voltage
T
MIN
to T
MAX
2.0 2.0 2.0 V
Logic Input Low Voltage
T
MIN
to T
MAX
0.8 0.8 0.7 V
Logic Input Current (Either Input) 50 50 50 µA
POWER SUPPLY CHARACTERISTICS
Operating Voltage Range +5, –10.8 ±18 +5, –10.8 ±18 +5, –10.8 ±18 V
Supply Current, R
L
= ∞ 610610610mA
Power Supply Rejection, Sample Mode 70 70 70 dB
TEMPERATURE RANGE
Specified Performance 0 +70 –25 +85 –55 +125 °C
PACKAGE OPTIONS
3, 4
Cerdip (Q-14) AD585AQ AD585SQ
LCC (E-20A) AD585SE
PLCC (P-20A) AD585JP
(typical @ +258C and V
S
= 612 V or 615 V, and C
H
= Internal, A = +1,
HOLD active unless otherwise noted)
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical
test. Results from those tests are used to calculate outgoing quality levels.
All min and max specifications are
guaranteed, although only those shown in
boldface are tested on all production units.
NOTES
1
Maximum input signal is the minimum supply minus a headroom voltage of 2.5 V.
2
Not tested at –55°C.
3
E = Leadless Ceramic Chip Carrier; P = Plastic Leaded Chip Carrier; Q = Cerdip.
4
For AD585/883B specifications, refer to Analog Devices Military Products Databook.
REV. A
–2–