Datasheet

AD5791 Data Sheet
Rev. D | Page 4 of 28
A, B Version
1
Parameter Min Typ Max Unit Test Conditions/Comments
Midscale Glitch Impulse
8
3.1 nV-sec V
REFP
= +10 V, V
REFN
= −10 V
1.7
nV-sec
V
REFP
= 10 V, V
REFN
= 0 V
1.4 nV-sec V
REFP
= 5 V, V
REFN
= 0 V
MSB Segment Glitch Impulse
8
9.1 nV-sec V
REFP
= +10 V, V
REFN
= −10 V, see Figure 42
3.6 nV-sec V
REFP
= 10 V, V
REFN
= 0 V, see Figure 43
1.9 nV-sec V
REFP
= 5 V, V
REFN
= 0 V, see Figure 44
Output Enabled Glitch Impulse 45 nV-sec On removal of output ground clamp
Digital Feedthrough 0.4 nV-sec
DC Output Impedance (Normal Mode) 3.4 kΩ
DC Output Impedance (Output Clamped
to Ground)
6 kΩ
Spurious Free Dynamic Range 100 dB 1 kHz tone, 10 kHz sample rate
Total Harmonic Distortion 97 dB 1 kHz tone, 10 kHz sample rate
REFERENCE INPUTS
3
V
REFP
Input Range 5 V
DD
− 2.5 V V
V
REFN
Input Range V
SS
+ 2.5 V 0
DC Input Impedance 5 6.6 kΩ V
REFP
, V
REFN
, code dependent,
typical at midscale code
Input Capacitance 15 pF V
REFP
, V
REFN
LOGIC INPUTS
3
Input Current
9
−1 +1 µA
Input Low Voltage, V
IL
0.3 × IOV
CC
V IOV
CC
= 1.71 V to 5.5 V
Input High Voltage, V
IH
0.7 × IOV
CC
V IOV
CC
= 1.71 V to 5.5 V
Pin Capacitance 5 pF
LOGIC OUTPUT (SDO)
3
Output Low Voltage, V
OL
0.4 V IOV
CC
= 1.71 V to 5.5 V, sinking 1 mA
Output High Voltage, V
OH
IOV
CC
− 0.5 V V IOV
CC
= 1.71 V to 5.5 V, sourcing 1 mA
High Impedance Leakage Current ±1 µA
High Impedance Output Capacitance 3 pF
POWER REQUIREMENTS All digital inputs at DGND or IOV
CC
V
DD
7.5 V
SS
+ 33 V
V
SS
V
DD
− 33 −2.5 V
V
CC
2.7
5.5
V
IOV
CC
1.71 5.5 V IOV
CC
≤ V
CC
I
DD
4.2 5.2 mA
I
SS
4 4.9 mA
I
CC
600 900 µA
IOI
CC
52 140 µA SDO disabled
DC Power Supply Rejection Ratio
3, 10
±0.6 µV/V V
DD
± 10%, V
SS
= 15 V
±0.6 µV/V V
SS
± 10%, V
DD
= 15 V
AC Power Supply Rejection Ratio
3
95
dB
V
DD
± 200 mV, 50 Hz/60 Hz, V
SS
= −15 V
95 dB ∆V
SS
± 200 mV, 50 Hz/60 Hz, V
DD
= 15 V
1
Temperature range: −40°C to +125°C, typical at +25°C and V
DD
= +15 V, V
SS
= −15 V, V
REFP
= +10 V, V
REFN
= −10 V.
2
Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer.
3
Guaranteed by design and characterization, not production tested.
4
Valid for all voltage reference spans.
5
Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified.
6
AD5791 configured in X2 gain mode, 25 pF compensation capacitor on AD797.
7
Includes noise contribution from AD8676BRZ voltage reference buffers.
8
The AD5791 is configured in bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF.(total capacitance seen by the output buffer, lead
capacitance, and so forth).
9
Current flowing in an individual logic pin.
10
Includes PSRR of AD8676BRZ voltage reference buffers.