Datasheet

AD5781 Data Sheet
Rev. D | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
4
5
6
7
8
9
10
V
OUT
V
REFPS
V
REFPF
CLR
RESET
V
DD
INV
IOV
CC
V
CC
LDAC
20
19
18
17
16
15
14
13
12
11
AGND
V
SS
V
REFNS
SYNC
DGND
V
REFNF
SDO
SDIN
SCLK
R
FB
AD5781
TOP VIEW
(Not to Scale)
09092-005
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 INV Connection to Inverting Input of External Amplifier. See the AD5781 Features section for further details.
2 V
OUT
Analog Output Voltage.
3 V
REFPS
Positive Reference Sense Voltage Input. A voltage range of 5 V to V
DD
− 2.5 V can be connected. A unity gain amplifier
must be connected at this pin, in conjunction with the V
REFPF
pin. See the AD5781 Features section for further details.
4 V
REFPF
Positive Reference Force Voltage Input. A voltage range of 5 V to V
DD
− 2.5 V can be connected. A unity gain amplifier
must be connected at these pin, in conjunction with the V
REFPS
pin. See AD5781 Features section for further details.
5 V
DD
Positive Analog Supply Connection. A voltage range of 7.5 V to 16.5 V can be connected. V
DD
should be decoupled to
AGND.
6
RESET
Active Low Reset Logic Input Pin. Asserting this pin returns the AD5781 to its power-on status.
7
CLR
Active Low Clear Logic Input Pin. Asserting this pin sets the DAC register to a user defined value (see Table 13) and
updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos
complement.
8
LDAC
Active Low Load DAC Logic Input Pin. This is used to update the DAC register and, consequently, the analog output.
When tied permanently low, the output is updated on the rising edge of
SYNC
. If
LDAC
is held high during the write
cycle, the input register is updated, but the output update is held off until the falling edge of
LDAC
. The
LDAC
pin
should not be left unconnected.
9 V
CC
Digital Supply Connection. A voltage in the range of 2.7 V to 5.5 V can be connected. V
CC
should be decoupled to DGND.
10 IOV
CC
Digital Interface Supply Pin. Digital threshold levels are referenced to the voltage applied to this pin. A voltage range of
1.71 V to 5.5 V can be connected. IOV
CC
should not be allowed to exceed V
CC
.
11 SDO Serial Data Output Pin. Data is clocked out on the rising edge of the serial clock input.
12
SDIN
Serial Data Input Pin. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
transferred at clock rates of up to 35 MHz.
14
SYNC
Active Low Digital Interface Synchronization Input Pin. This is the frame synchronization signal for the input data. When
SYNC
is low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks.
The input shift register is updated on the rising edge of
SYNC
.
15 DGND Ground Reference Pin for Digital Circuitry.
16 V
REFNF
Negative Reference Force Voltage Input. A voltage range of V
SS
+ 2.5 V to 0 V can be connected. A unity gain amplifier
must be connected at this pin, in conjunction with the V
REFNS
pin. See the AD5781 Features section for further details.
17 V
REFNS
Negative Reference Sense Voltage Input. A voltage range of V
SS
+ 2.5 V to 0 V can be connected. A unity gain amplifier
must be connected at these pin, in conjunction with the V
REFNF
pin. See the AD5781 Features section for further details.
18 V
SS
Negative Analog Supply Connection. A voltage range of −16.5 V to −2.5 V can be connected. V
SS
should be decoupled to
AGND.
19 AGND Ground Reference Pin for Analog Circuitry.
20 R
FB
Feedback Connection for External Amplifier. See the AD5781 Features section for further details.