Datasheet

Data Sheet AD5781
Rev. D | Page 19 of 28
THEORY OF OPERATION
The AD5781 is a high accuracy, fast settling, single, 18-bit,
serial input, voltage output DAC. It operates from a V
DD
supply
voltage of 7.5 V to 16.5 V and a V
SS
supply of −16.5 V to −2.5 V.
Data is written to the AD5781 in a 24-bit word format via a 3-wire
serial interface. The AD5781 incorporates a power-on reset
circuit that ensures the DAC output powers up to 0 V with the
V
OUT
pin clamped to AGND through a ~6 kΩ internal resistor.
DAC ARCHITECTURE
The architecture of the AD5781 consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 49.
The six MSBs of the 18-bit data-word are decoded to drive 63
switches, E0 to E62. Each of these switches connects one of 63
matched resistors to either the V
REFP
or V
REFN
voltage. The
remaining 12 bits of the data-word drive the S0 to S11 switches
of a 12-bit voltage mode R-R ladder network.
2R
S0
2R
S1
2R
S11
2R
E62
2R
E61
2R
E0
12-BIT R-R LADDER
.....................
.....................
..........
..........
RR
R
2R
V
REFPF
V
REFPS
V
REFNF
V
REFNS
V
OUT
SIX MSBs DECODED INTO
63 EQUAL SEGMENTS
09092-053
Figure 49. DAC Ladder Structure Serial Interface
The AD5781 has a 3-wire serial interface (
SYNC
, SCLK, and
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see Figure 2 for a
timing diagram).
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK, which can operate at up to 35 MHz. The
input register consists of a R/
W
bit, three address bits, and
twenty data bits as shown in Table 7. The timing diagram for
this operation is shown in Figure 2.
Table 7. Input Shift Register Format
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB0
R/W
Register address Register data
Table 8. Decoding the Input Shift Register
R/
W
Register Address Description
X
1
0 0 0 No operation (NOP). Used in readback operations.
0 0 0 1 Write to the DAC register.
0 0 1 0 Write to the control register.
0 0 1 1 Write to the clearcode register.
0 1 0 0 Write to the software control register.
1 0 0 1 Read from the DAC register.
1 0 1 0 Read from the control register.
1 0 1 1 Read from the clearcode register.
1
X is don’t care.