Datasheet

Data Sheet AD5764R
Rev. D | Page 25 of 32
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select the DAC channel with which the data
transfer takes place (see Ta ble 10). The data bits are positioned in DB15 to DB0, as shown in Table 13.
Table 13. Programming the Data Register
REG2 REG1 REG0 A2 A1 A0 DB15 to DB0
0 1 0 DAC address 16-bit DAC data
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select the DAC channel with which the
data transfer takes place (see Table 10). The coarse gain register is a 2-bit register that allows the user to select the output range of each
DAC, as shown in Table 15.
Table 14. Programming the Coarse Gain Register
REG2 REG1 REG0 A2 A1 A0 DB15 to DB2 DB1 DB0
0 1 1 DAC address Don’t care CG1 CG0
Table 15. Output Range Selection
Output Range CG1 CG0
±10 V (Default) 0 0
±10.2564 V 0 1
±10.5263 V 1 0
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select the DAC channel with which the data
transfer takes place (see Ta ble 10). The AD5764R fine gain register is a 6-bit register that allows the user to adjust the gain of each DAC
channel by −32 LSBs to +31 LSBs in 1 LSB steps, as shown in Table 16 and Tabl e 17. The adjustment is made to both the positive full-scale
points and the negative full-scale points simultaneously, with each point adjusted by one-half of one step. The fine gain register coding is
twos complement.
Table 16. Programming the Fine Gain Register
REG2 REG1 REG0 A2 A1 A0 DB15 to DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 0 DAC address Don’t care FG5 FG4 FG3 FG2 FG1 FG0
Table 17. Fine Gain Register Options
Gain Adjustment FG5 FG4 FG3 FG2 FG1 FG0
+31 LSBs 0 1 1 1 1 1
+30 LSBs 0 1 1 1 1 0
No Adjustment (Default) 0 0 0 0 0 0
−31 LSBs 1 0 0 0 0 1
−32 LSBs 1 0 0 0 0 0