Datasheet

Data Sheet AD5764R
Rev. D | Page 23 of 32
See Figure 41 for a simplified block diagram of the DAC load
circuitry.
VOUTx
DATA
REGISTER
INTERFACE
LOGIC
OUTPUT
I/V AMPLIFIER
LDAC
SDO
SDIN
16-BIT
DAC
REFAB, REFCD
SYNC
INPUT
REGISTER
SCLK
06064-062
Figure 41. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
TRANSFER FUNCTION
Table 7 and Table 8 show the ideal input code to output voltage
relationship for offset binary data coding and twos complement
data coding, respectively.
The output voltage expression for the AD5764R is given by






×+×−=
536,65
42
D
VVV
REFINREFIN
OUT
where:
D is the decimal equivalent of the code loaded to the DAC.
V
REFIN
is the reference voltage applied at the REFAB and
REFCD pins.
ASYNCHRONOUS CLEAR (CLR)
CLR
is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain
CLR
low for a minimum amount of time for the operation to complete
(see
Figure 2). When the
CLR
signal is returned high, the output
remains at the cleared value until a new value is programmed.
If
CLR
is at 0 V at power-on, all DAC outputs are updated with
the clear value. A clear can also be initiated through software by
writing the command of 0x04XXXX.
Table 7. Ideal Output Voltage to Input Code Relationship—Offset Binary Data Coding
Digital Input Analog Output
MSB
LSB
V
OUT
1111 1111 1111 1111 +2 V
REFIN
× (32,767/32,768)
1000 0000 0000 0001 +2 V
REFIN
× (1/32,768)
1000 0000 0000 0000 0 V
0111 1111 1111 1111 −2 V
REFIN
× (1/32,768)
0000 0000 0000 0000 −2 V
REFIN
× (32,767/32,768)
Table 8. Ideal Output Voltage to Input Code Relationship—Twos Complement Data Coding
Digital Input Analog Output
MSB LSB V
OUT
0111 1111 1111 1111 +2 V
REFIN
× (32,767/32,768)
0000 0000 0000 0001 +2 V
REFIN
× (1/32,768)
0000 0000 0000 0000 0 V
1111 1111 1111 1111 −2 V
REFIN
× (1/32,768)
1000 0000 0000 0000 −2 V
REFIN
× (32,767/32,768)