Datasheet

AD5764 Data Sheet
Rev. F | Page 20 of 28
The output voltage expression for the AD5764 is given by
TRANSFER FUNCTION
⎥
⎦
⎤
⎢
⎣
⎡
×+×−=
536,65
42
D
VVV
REFINREFIN
OUT
Table 7 and Table 8 show the ideal input code to output voltage
relationship for the AD5764 for both offset binary and twos
complement data coding, respectively.
where:
D is the decimal equivalent of the code loaded to the DAC.
V
REFIN
is the reference voltage applied at the REFAB/REFCD pins.
Table 7. Ideal Output Voltage to Input Code Relationship—
Offset Binary Data Coding
Digital Input Analog Output
ASYNCHRONOUS CLEAR (CLR)
MSB LSB VOUTx
1111 1111 1111 1111 +2 V
REF
× (32,767/32,768)
CLR
is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain
CLR
low for a minimum amount of time (see ) for the operation
to complete. When the
Figure 2
CLR
signal is returned high, the output
remains at the cleared value until a new value is programmed. If
at power-on,
CLR
is at 0 V, then all DAC outputs are updated
with the clear value. A clear can also be initiated through software
by writing Command 0x04XXXX to the AD5764.
1000 0000 0000 0001 +2 V
REF
× (1/32,768)
1000 0000 0000 0000 0 V
0111 1111 1111 1111
−2 V
REF
× (1/32,768)
0000 0000 0000 0000 −2 V
REF
× (32,767/32,768)
Table 8. Ideal Output Voltage to Input Code Relationship—
Twos Complement Data Coding
Digital Input Analog Output
MSB LSB VOUTx
0111 1111 1111 1111 +2 V
REF
× (32,767/32,768)
0000 0000 0000 0001 +2 V
REF
× (1/32,768)
0000 0000 0000 0000
0 V
1111 1111 1111 1111
−2 V
REF
× (1/32,768)
1000 0000 0000 0000 −2 V
REF
× (32,767/32,768)
Table 9. Input Shift Register Bit Map
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15:DB0
R/W
0 REG2 REG1 REG0 A2 A1 A0 Data
Table 10. Input Shift Register Bit Functions
Bit Description
R/W
Indicates a read from or a write to the addressed register.
REG2, REG1, REG0
Used in association with the address bits to determine if a read or write operation is to the data register, offset
register, coarse gain register, fine gain register, or function register.
REG2 REG1 REG0 Function
0 0 0 Function register
0 1 0 Data register
0 1 1 Coarse gain register
1 0 0 Fine gain register
1 0 1 Offset register
A2, A1, A0 These bits are used to decode the DAC channels.
A2 A1 A0 Channel Address
0 0 0 DAC A
0 0 1 DAC B
0 1 0 DAC C
0 1 1 DAC D
1 0 0 All DACs
Data Data bits.