Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Product Highlights
- Companion Products
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Theory of Operation
- AD5760 Features
- Applications Information
- Outline Dimensions

Data Sheet AD5760
Rev. D | Page 21 of 28
Table 8. Hardware Control Pins Truth Table
LDAC
CLR
RESET
Function
X
1
X
1
0 The AD5760 is in reset mode. The device cannot be programmed.
X
1
X
1
The AD5760 is returned to its power-on state. All registers are set to their default values.
0 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly.
0 1 1 The output is set according to the DAC register value.
1 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly.
1 1 The output is set according to the DAC register value.
0 1 The output remains at the clearcode register value.
1 1 The output remains set according to the DAC register value.
0 1 The output remains at the clearcode register value.
1
1
The DAC register is loaded with the clearcode register value and the output is set accordingly.
0
1 The DAC register is loaded with the clearcode register value and the output is set accordingly.
1
1 The output remains at the clearcode register value.
0
1 The output is set according to the DAC register value.
1
X is don’t care.
Table 9. DAC Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 to DB4 DB3 DB2 DB1 DB0
R/
W
Register address DAC register data
R/
W
0 0 1 16 bits of data X
1
X
1
X
1
X
1
1
X is don’t care.