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Ultra Stable, 16-

Bit ±0.5 LSB INL,

Voltage Output DAC

Data Sheet

AD5760

Rev. D Document Feedback

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FEATURES

True 16-bit voltage output DAC, ±0.5 LSB INL

8 nV/√Hz output noise spectral density

0.00625 LSB long-term linearity error stability

±0.018 ppm/°C gain error temperature coefficient

2.5 µs output voltage settling time

3.5 nV-sec midscale glitch impulse

Integrated precision reference buffers

Operating temperature range: −40°C to +125°C

4 mm × 5 mm LFCSP package

Wide power supply range of up to ±16.5 V

35 MHz Schmitt triggered digital interface

1.8 V-compatible digital interface

APPLICATIONS

Medical instrumentation

Test and measurement

Industrial control

Scientific and aerospace instrumentation

Data acquisition systems

Digital gain and offset adjustment

Power supply control

FUNCTIONAL BLOCK DIAGRAM

6.8kΩ

6kΩ

6.8kΩ

R1 R

DAC

REG

1616

INPUT

SHIFT

AND

CONTROL

LOGIC

POWER-ON RESET

AND CLEAR LOGIC

AD5760

IOV

SDIN

REFP

AGND

DGND

SCLK

SYNC

SDO

LDAC

CLR

RESET

INV

OUT

16-BIT

DAC

REFN

09650-001

Figure 1.

Table 1. Related Devices

Part No. Description

AD5790 20-bit, 2 LSB accurate DAC

AD5791 20-bit, 1 LSB accurate DAC

AD5780 18-bit, 1 LSB accurate DAC

AD5781 18-bit, 0.5 LSB INL

AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC

GENERAL DESCRIPTION

The AD5760

is a true 16-bit, unbuffered voltage output DAC

that operates from a bipolar supply of up to 33 V. The AD5760

accepts a positive reference input range of 5 V to V

− 2.5 V

and a negative reference input range of V

+ 2.5 V to 0 V. The

AD5760 offers a relative accuracy specification of ±0.5 LSB

maximum range, and operation is guaranteed monotonic with

a ±0.5 LSB DNL maximum range specification.

The part uses a versatile 3-wire serial interface that operates at

clock rates of up to 35 MHz and is compatible with standard

SPI, QSPI™, MICROWIRE™, and DSP interface standards. The

part incorporates a power-on reset circuit that ensures that the

DAC output powers up to 0 V in a known output impedance

state and remains in this state until a valid write to the device

takes place. The part provides an output clamp feature that

places the output in a defined load state.

Protected by U.S. Patent No. 7,884,747 and 8,089,380.

PRODUCT HIGHLIGHTS

1. True 16-bit accuracy.

2. Wide power supply range of up to ±16.5 V.

3. −40°C to +125°C operating temperature range.

4. Low 8 nV/√Hz noise.

5. Low ±0.018 ppm/°C gain error temperature coefficient.

COMPANION PRODUCTS

Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1

External Reference: ADR445

DC-to-DC Design Tool: ADIsimPower™

Additional companion products on the AD5780 product page

Summary of content (28 pages)

PAGE 1
Ultra Stable, 16-Bit ±0.5 LSB INL, Voltage Output DAC AD5760 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD VCC VREFP A1 IOVCC SDIN SCLK SYNC SDO R1 CLR RFB RFB INV INPUT SHIFT REGISTER AND CONTROL LOGIC 16 DAC REG 16 16-BIT DAC VOUT 6kΩ LDAC RESET 6.8kΩ 6.8kΩ POWER-ON RESET AND CLEAR LOGIC DGND VSS AD5760 VREFN AGND 09650-001 True 16-bit voltage output DAC, ±0.5 LSB INL 8 nV/√Hz output noise spectral density 0.00625 LSB long-term linearity error stability ±0.
PAGE 2
AD5760 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DAC Architecture....................................................................... 19 Applications ....................................................................................... 1 Serial Interface ............................................................................ 19 Functional Block Diagram ................................................
PAGE 3
Data Sheet AD5760 SPECIFICATIONS VDD = +12.5 V to +16.5 V, VSS = −16.5 V to −12.5 V, VREFP = +10 V, VREFN = −10 V, VCC = 2.7 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 4
AD5760 Parameter REFERENCE INPUTS VREFP Input Range VREFN Input Range Input Bias Current Input Capacitance LOGIC INPUTS Input Current 5 Input Low Voltage, VIL Input High Voltage, VIH Pin Capacitance LOGIC OUTPUT (SDO) Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance POWER REQUIREMENTS VDD VSS VCC IOVCC IDD ISS ICC IOICC DC Power Supply Rejection Ratio AC Power Supply Rejection Ratio Data Sheet Min 5 VSS + 2.
PAGE 5
Data Sheet AD5760 TIMING CHARACTERISTICS VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 1 2 Limit 1 IOVCC = 1.71 V to 3.3 V IOVCC = 3.3 V to 5.
PAGE 6
AD5760 Data Sheet t7 t1 SCLK 1 2 24 t3 t6 t2 t4 t5 SYNC t9 t8 SDIN DB23 DB0 t10 t12 t11 LDAC t13 VOUT t14 VOUT t15 CLR t16 VOUT t21 RESET 09650-002 t22 VOUT Figure 2. Write Mode Timing Diagram t1 t17 SCLK 1 2 24 t3 t6 t20 t7 1 2 24 t2 t5 t4 t5 t17 SYNC SDIN t9 DB23 DB0 INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION t18 t19 DB23 SDO REGISTER CONTENTS CLOCKED OUT Figure 3. Readback Mode Timing Diagram Rev.
PAGE 7
Data Sheet AD5760 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4.
PAGE 8
AD5760 Data Sheet 24 23 22 21 20 INV DNC DNC DNC RFB PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD5760 TOP VIEW (Not to Scale) 19 18 17 16 15 14 13 AGND VSS VSS VREFN DGND SYNC SCLK NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. NEGATIVE ANALOG SUPPLY CONNECTION (VSS). A VOLTAGE IN THE RANGE OF –16.5 V TO –2.5 V CAN BE CONNECTED. VSS SHOULD BE DECOUPLED TO AGND. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE VSS PINS.
PAGE 9
Data Sheet Pin No. 20 24 EPAD Mnemonic RFB INV VSS AD5760 Description Feedback Connection for External Amplifier. See the AD5760 Features section for further details. Inverting Input Connection for External Amplifier. See the AD5760 Features section for further details. Negative Analog Supply Connection (VSS). A voltage in the range of −16.5 V to −2.5 V can be connected to this pin. VSS must be decoupled to AGND.
PAGE 10
AD5760 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.10 VREFP = +5V VREFN = 0V VDD = +15V 0.05 VSS = –15V VREFP = +10V VREFN = –10V VDD = +15V VSS = –15V 0.08 0.06 0 0.02 INL (LSB) 0 –0.02 –0.05 –0.10 –0.04 –0.06 –0.15 –0.08 10000 0 20000 30000 40000 50000 60000 70000 DAC CODE Figure 5. Integral Nonlinearity Error vs. DAC Code, ±10 V Span 0.15 –0.20 09650-006 –0.10 AD8675 OUTPUT BUFFER TA = 25°C 0 10000 20000 30000 40000 50000 60000 70000 DAC CODE Figure 8.
PAGE 11
Data Sheet AD5760 0.10 0.09 VREFP = +5V VREFN = 0V VDD = +15V VSS = –15V 0.08 0.06 VDD = +15V VSS = –15V AD8675 OUTPUT BUFFER 0.07 DNL ERROR (LSB) 0.02 0 –0.02 –0.04 0.05 ±10V SPAN MAX INL +10V SPAN MAX INL +5V SPAN MAX INL 0.03 ±10V SPAN MIN INL +10V SPAN MIN INL +5V SPAN MIN INL 0.01 –0.06 40000 50000 60000 70000 DAC CODE –0.01 –40 09650-012 –0.08 AD8675 OUTPUT BUFFER TA = 25°C –0.10 0 10000 20000 30000 –20 0 20 40 60 TEMPERATURE (°C) 80 100 09650-014 DNL (LSB) 0.
PAGE 12
AD5760 Data Sheet 0.8 0.09 0.08 DNL MAX 0.6 ZERO-SCALE ERROR (LSB) 0.07 TA = 25°C VREFP = +10V VREFN = –10V AD8675 OUTPUT BUFFER 0.05 0.04 0.03 0.02 0.01 0.4 0.2 0 –0.2 13.0 13.5 14.0 14.5 15.0 VDD/|VSS| (V) 15.5 16.0 16.5 –0.4 7.5 09650-018 –0.01 12.5 Figure 17. Differential Nonlinearity Error vs. Supply Voltage, ±10 V Span 14.5 15.5 16.5 –0.04 0.06 TA = 25°C VREFP = 5V VREFN = 0V AD8675 OUTPUT BUFFER 0.03 0.02 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.
PAGE 13
Data Sheet AD5760 0.14 0.38 TA = 25°C VREFP = 5V VREFN = 0V 0.36 AD8675 OUTPUT BUFFER 0.10 GAIN ERROR (LSB) 0.08 0.06 0.04 0.34 0.32 0.30 13.0 13.5 15.0 14.5 14.0 VDD/|VSS| (V) 15.5 16.0 16.5 09650-024 0 12.5 0.26 7.5 8.5 10.5 11.5 12.5 13.5 VDD/|VSS| (V) 14.5 15.5 16.5 Figure 26. Gain Error vs. Supply Voltage, 5 V Span 0.5 0.08 TA = 25°C VREFP = 5V 0.3 VREFN = 0V AD8675 OUTPUT BUFFER 0.06 INL MAX 0.04 0.1 INL ERROR (LSB) FULL-SCALE ERROR (LSB) Figure 23.
PAGE 14
AD5760 Data Sheet –0.02 –0.03 –0.30 –0.04 GAIN ERROR (LSB) –0.05 –0.06 –0.07 –0.35 –0.40 –0.08 –0.45 TA = 25°C VDD = +15V VSS = –15V AD8675 OUTPUT BUFFER –0.09 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 VREFP /|VREFN | (V) –0.50 5.0 09650-030 –0.10 5.0 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 VREFP /|VREFN | (V) Figure 32. Gain Error vs. Reference Voltage Figure 29. Zero-Scale Error vs. Reference Voltage 0.50 –0.05 TA = 25°C –0.
PAGE 15
Data Sheet AD5760 0.4 0.010 ±10V SPAN +10V SPAN +5V SPAN 0.008 IDD 0.006 0.004 IDD/ISS (mA) 0 –0.2 0.002 0 –0.002 –0.4 –0.004 –0.006 –0.8 –40 VDD = +15V VSS = –15V AD8675 OUTPUT BUFFER –20 0 20 40 60 80 100 TEMPERATURE (°C) –0.010 –20 Figure 35. Zero-Scale Error vs. Temperature 0 –15 –10 –5 0 5 VDD/VSS (V) 10 15 20 Figure 38. Power Supply Currents vs. Power Supply Voltages 6 ±10V SPAN +10V SPAN +5V SPAN –0.1 ISS –0.008 09650-039 –0.6 09650-036 ZERO-SCALE ERROR (LSB) 0.
PAGE 16
AD5760 Data Sheet 6 10 VREFP = 5V VREFN = 0V UNITY-GAIN MODE 5 ADA4898-1 RC LOW-PASS FILTER 9 OUTPUT GLITCH (nV-s) 8 6 5 4 3 VREFP = +10V VREFN = –10V RC LOW-PASS FILTER UNITY-GAIN MODE ADA4898-1 0 –1 0 1 2 3 4 3 2 1 5 TIME (µs) 0 09650-046 1 09650-042 2 4 16384 65536 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 VOUT (mV) 7 NEGATIVE POSITIVE CODE Figure 44.
PAGE 17
Data Sheet AD5760 0.20 VDD = +15V VSS = –15V VREFP = +10V VREFN = –10V VDD = +15V VSS = –15V VREFP = +10V VREFN = –10V UNITY GAIN ADA4898-1 0.18 OUTPUT VOLTAGE (V) 0.16 10 0.14 0.12 0.10 0.08 0.06 0.04 0.02 1 10 100 1k FREQUENCY (Hz) 10k Figure 47. Noise Spectral Density vs. Frequency –0.02 0 1 2 3 4 5 TIME (µs) Figure 48. Glitch Impulse on Removal of Output Clamp Rev. D | Page 17 of 28 6 09650-049 0 1 0.
PAGE 18
AD5760 Data Sheet TERMINOLOGY Relative Accuracy Relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. A typical INL error vs. code plot is shown in Figure 5. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
PAGE 19
Data Sheet AD5760 THEORY OF OPERATION R 2R VREFP R R VOUT 2R 2R ... 2R 2R 2R ... 2R S0 S1 ... S9 E62 E61... E0 VREFN 10-BIT R-2R LADDER DAC ARCHITECTURE 09650-050 The AD5760 is a high accuracy, fast settling, single, 16-bit, serial input, voltage output DAC. It operates from a VDD supply voltage of 7.5 V to 16.5 V and a VSS supply of −16.5 V to −2.5 V. Data is written to the AD5760 in a 24-bit word format via a 3-wire serial interface.
PAGE 20
AD5760 Data Sheet Standalone Operation Synchronous DAC Update The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can be used only if SYNC is held low for the correct number of clock cycles. In this mode, LDAC is held low while data is being clocked into the input shift register. The DAC output is updated on the rising edge of SYNC.
PAGE 21
Data Sheet AD5760 Table 8. Hardware Control Pins Truth Table LDAC X1 X1 0 0 1 CLR X1 X1 0 1 0 1 0 1 0 RESET 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 Function The AD5760 is in reset mode. The device cannot be programmed. The AD5760 is returned to its power-on state. All registers are set to their default values. The DAC register is loaded with the clearcode register value, and the output is set accordingly. The output is set according to the DAC register value.
PAGE 22
AD5760 Data Sheet Control Register is asserted. The output value depends on the DAC coding that is being used, either binary or twos complement. The default register value is 0. The control register controls the mode of operation of the AD5760. Clearcode Register The clearcode register sets the value to which the DAC output is set when the CLR pin or CLR bit in the software control register Table 10.
PAGE 23
Data Sheet AD5760 Software Control Register This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low. Table 13. Software Control Register MSB DB23 R/W DB22 0 1 1 2 LSB DB21 DB20 Register address 0 0 DB19 to DB3 Reserved DB2 DB1 Software control register data Reset CLR 1 DB0 LDAC 2 The CLR function has no effect when the LDAC pin is low. The LDAC function has no effect when the CLR pin is low. Table 14.
PAGE 24
AD5760 Data Sheet AD5760 FEATURES The AD5760 contains a power-on reset circuit that, as well as resetting all registers to their default values, controls the output voltage during power-up. Upon power-on, the DAC is placed in tristate (its reference inputs are disconnected), and its output is clamped to AGND through a ~6 kΩ resistor. The DAC remains in this state until programmed otherwise via the control register.
PAGE 25
Data Sheet AD5760 Gain of Two Configuration (×2 Gain Mode) VREFP Rev. D | Page 25 of 28 A1 6.8kΩ 6.8kΩ R1 16-BIT DAC RFB RFB INV 10pF VOUT VOUT AD8675 ADA4898-1 ADA4004-1 AD5760 VREFN Figure 52. Output Amplifier in Gain of Two Configuration 09650-054 Figure 52 shows an output amplifier configured for a gain of two. The gain is set by the internal matched 6.
PAGE 26
AD5760 Data Sheet APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT 09650-055 Figure 53. Typical Operating Circuit Rev.
PAGE 27
Data Sheet Figure 53 shows a typical operating circuit for the AD5760 using an AD8675 as an output buffer. Because the output impedance of the AD5760 is 3.4 kΩ, an output buffer is required for driving low resistive, high capacitive loads. EVALUATION BOARD Refer to the evaluation board available for the AD5780 or AD5790 to evaluate a 18-bit version or 20-bit version of the AD5760.
PAGE 28
AD5760 Data Sheet OUTLINE DIMENSIONS 2.75 2.65 2.50 4.00 BSC PIN 1 INDICATOR 20 PIN 1 INDICATOR 1 19 0.50 BSC 3.75 3.65 3.50 EXPOSED PAD 7 13 TOP VIEW 1.00 0.90 0.80 SEATING PLANE 0.30 0.25 0.20 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 8 12 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 04-11-2012-B 5.00 BSC (Chamfer 0.225) 24 Figure 54.