Datasheet

AD5757 Data Sheet
Rev. D | Page 32 of 44
Slew Rate Control Register
This register is used to program the slew rate control for the
selected DAC channel. The slew rate control is enabled/
disabled and programmed on a per channel basis. See Table 25
and the Digital Slew Rate Control section for more information.
READBACK OPERATION
Readback mode is invoked by setting the R/
W
bit = 1 in the
serial input register write. See Table 26 for the bits associated
with a readback operation. The DUT_AD1 and DUT_AD0 bits,
in association with Bits RD[4:0], select the register to be read.
The remaining data bits in the write sequence are don’t cares.
During the next SPI transfer (see Figure 4), the data appearing
on the SDO output contains the data from the previously
addressed register. This second SPI transfer should either be a
request to read yet another register on a third data transfer or a
no operation command. The no operation command for
DUT_AD[1:0] = 00 is 0x1CE000; for other DUT addresses,
Bit D22 and Bit D21 are set accordingly.
Readback Example
To read back the gain register of Device 1, Channel A on the
AD5757, implement the following sequence:
1. Write 0xA80000 to the AD5757 input register. This
configures the AD5757 Device Address 1 for read mode
with the gain register of Channel A selected. All the data
bits, D15 to D0, are don’t cares.
2. Follow with another read command or a no operation
command (0x3CE000). During this command, the data
from the Channel A gain register is clocked out on the
SDO line.
Table 25. Programming the Slew Rate Control Register
D15 D14 D13 D12 D11 to D7 D6 to D3 D2 to D0
0 0 0 SREN X
1
SR_CLOCK SR_STEP
1
X = don’t care.
Table 26. Input Shift Register Contents for a Read Operation
D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0
R/
W
DUT_AD1
DUT_AD0
RD4
RD3
RD2
RD1
RD0
X
1
1
X = don’t care.
Table 27. Read Address Decoding
RD4
RD3
RD2
RD1
RD0
Function
0 0 0 0 0 Read DAC A data register
0 0 0 0 1 Read DAC B data register
0 0 0 1 0 Read DAC C data register
0 0 0 1 1 Read DAC D data register
0 0 1 0 0 Read DAC A control register
0 0 1 0 1 Read DAC B control register
0 0 1 1 0 Read DAC C control register
0 0 1 1 1 Read DAC D control register
0 1 0 0 0 Read DAC A gain register
0 1 0 0 1 Read DAC B gain register
0 1 0 1 0 Read DAC C gain register
0
1
0
1
1
Read DAC D gain register
0 1 1 0 0 Read DACA offset register
0 1 1 0 1 Read DAC B offset register
0 1 1 1 0 Read DAC C offset register
0 1 1 1 1 Read DAC D offset register
1
0
0
0
0
Clear DAC A code register
1 0 0 0 1 Clear DAC B code register
1 0 0 1 0 Clear DAC C code register
1 0 0 1 1 Clear DAC D code register
1 0 1 0 0 DAC A slew rate control register
1 0 1 0 1 DAC B slew rate control register
1 0 1 1 0 DAC C slew rate control register
1 0 1 1 1 DAC D slew rate control register
1 1 0 0 0 Read status register
1 1 0 0 1 Read main control register
1 1 0 1 0 Read dc-to-dc control register