Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA Output DAC, Dynamic Power Control, HART Connectivity AD5757 Data Sheet a dc-to-dc boost converter optimized for minimum on-chip power dissipation. FEATURES 16-bit resolution and monotonicity Dynamic power control for thermal management or external PMOS mode Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, or 0 mA to 24 mA ±0.
AD5757 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Readback Operation .................................................................. 32 Applications ....................................................................................... 1 Device Features ............................................................................... 34 General Description .....................................................
Data Sheet AD5757 REVISION HISTORY 11/12—Rev. C to Rev. D Changed Thermal Impedance from 20°C/W to 28°C/W ..........10 Changes to Pin 6 Description ........................................................11 Changes to DUT_AD1, DUT_AD0 Description, Table 8 .........27 Changes to Changes to Packet Error Checking Section and Internal Reference Section .............................................................35 Changes to Figure 57 ......................................................................
AD5757 Data Sheet DETAILED FUNCTIONAL BLOCK DIAGRAM AVCC 5.0V AGND DVDD DGND LDAC CLEAR SCLK SDIN SYNC SDO VBOOST_A DC-TO-DC CONVERTER POWER CONTROL INPUT SHIFT REGISTER AND CONTROL STATUS REGISTER REFOUT SWA POWER-ON RESET FAULT ALERT AVDD +15V 16 INPUT REG A + DAC REG A 16 7.4V TO 29.
Data Sheet AD5757 SPECIFICATIONS AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
AD5757 Parameter 1 Reference Output Output Voltage Reference TC2 Output Noise (0.1 Hz to 10 Hz)2 Noise Spectral Density2 Output Voltage Drift vs.
Data Sheet AD5757 AC PERFORMANCE CHARACTERISTICS AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 DYNAMIC PERFORMANCE Current Output Output Current Settling Time Output Noise (0.1 Hz to 10 Hz Bandwidth) Output Noise Spectral Density 1 Min Typ Max Unit Test Conditions/Comments 15 See test conditions/ comments 0.
AD5757 Data Sheet Timing Diagrams t1 SCLK 1 2 24 t3 t6 t2 t4 t5 SYNC t8 t7 SDIN t19 MSB LSB t10 t10 t9 LDAC t17 t12 t11 IOUT_x LDAC = 0 t12 t16 IOUT_x t13 CLEAR t14 IOUT_x 09225-002 t18 RESET Figure 3. Serial Interface Timing Diagram SCLK 1 1 24 24 t6 SYNC MSB LSB MSB LSB INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION MSB SDO LSB UNDEFINED t15 Figure 4. Readback Timing Diagram Rev.
Data Sheet LSB 1 AD5757 MSB 16 2 SCLK SDO R/W DUT_ AD1 DUT_ AD0 SDO DISABLED X X X D15 D14 D1 D0 SDO_ ENAB STATUS STATUS STATUS STATUS Figure 5. Status Readback During Write 200µA TO OUTPUT PIN IOL VOH (MIN) OR VOL (MAX) CL 50pF 200µA IOH Figure 6. Load Circuit for SDO Timing Diagram Rev.
AD5757 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4.
Data Sheet AD5757 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RSET_C RSET_D REFOUT REFIN NC CHARTD IGATED COMPDCDC_D VBOOST_D NC IOUT_D AGND NC CHARTC NC IGATEC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD5757 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COMPDCDC_C IOUT_C VBOOST_C AVCC SWC GNDSWC GNDSWD SWD AGND SWA GNDSWA GNDSWB SWB AGND VBOOST_B IOUT_B NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2.
AD5757 Data Sheet Pin No. 15 Mnemonic ALERT 16 FAULT 18 19 20, 25, 28, 30, 50, 52, 55, 60 21 22 RESET AVDD NC 23 COMPDCDC_A 24 VBOOST_A 26 27, 40, 53 29 31 IOUT_A AGND CHARTB IGATEB 32 COMPDCDC_B 33 34 IOUT_B VBOOST_B 35 36 AGND SWB 37 38 39 GNDSWB GNDSWA SWA 41 SWD 42 43 44 GNDSWD GNDSWC SWC 45 46 AVCC VBOOST_C 47 48 IOUT_C COMPDCDC_C 49 IGATEC CHARTA IGATEA Description Active High Output.
Data Sheet Pin No. 51 54 56 Mnemonic CHARTC IOUT_D VBOOST_D 57 COMPDCDC_D 58 IGATED 59 61 62 CHARTD REFIN REFOUT 63 RSET_D 64 RSET_C EPAD AD5757 Description HART Input Connection for DAC Channel C. Current Output Pin for DAC Channel D. Supply for Channel D Current Output Stage (see Figure 49). To use the dc-to-dc feature of the device, connect as shown in Figure 56. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground.
AD5757 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS CURRENT OUTPUTS 0.0025 0.0010 AV DD = 15V TA = 25°C 0.0008 0.0006 0.0010 0.0004 INL ERROR (%FSR) 0.0015 0.0005 0 –0.0005 –0.0010 –0.0020 20mA, 20mA, 20mA, 20mA, 20mA, –0.0025 0 10000 EXTERNAL R SET EXTERNAL R SET , WITH DC-TO-DC CONVERTER INTERNAL R SET INTERNAL R SET , WITH DC-TO-DC CONVERTER EXTERNAL R SET , EXTERNAL PMOS MODE 20000 40000 30000 50000 0 –0.
Data Sheet AD5757 0.03 0.02 0.01 0.01 0 –0.01 –0.02 –0.03 AVDD = 15V 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO –0.04 –0.05 –0.06 –0.07 –0.08 –40 –20 0 20mA INTERNAL RSET 20mA INTERNAL RSET 24mA INTERNAL RSET 20mA EXTERNAL RSET 20mA EXTERNAL RSET 24mA EXTERNAL RSET 60 40 20 TEMPERATURE (°C) –0.01 –0.02 AVDD = 15V –0.03 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO –0.04 –0.05 80 100 –0.06 –40 0.03 20 40 60 TEMPERATURE (°C) 80 100 0.0025 0.02 0.0020 0.
AD5757 Data Sheet 1.0 0.006 0.4 0.2 DNL ERROR MAX DNL ERROR MIN 0 –0.2 –0.4 –0.6 –0.8 15 20 25 30 SUPPLY (V) 0 –0.002 –0.006 –0.008 15 10 25 20 30 6 5 0.008 4 CURRENT (µA) 0.010 0.006 0.004 AVDD = 15V TA = 25°C RLOAD = 300Ω 3 2 4mA TO 20mA RANGE MAX TUE 4mA TO 20mA RANGE MIN TUE TA = 25°C 15 20 SUPPLY (V) 1 25 30 0 09225-060 0 10 MIN OF TUE –0.010 Figure 23. Total Unadjusted Error vs. VBOOST_X, Using External PMOS Mode 0.012 0.
AD5757 30 25 25 OUTPUT CURRENT (mA) 30 20 IOUT VBOOST 10 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) AVCC = 5V TA = 25°C 5 0 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 TIME (ms) 10 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 0 –0.25 0 0.25 0.75 0.50 1.00 1.25 1.50 1.75 TIME (ms) Figure 28. Output Current Settling with DC-to-DC Converter vs.
AD5757 Data Sheet 0 20mA OUTPUT 10mA OUTPUT 8 6 IOUT_x PSRR (dB) 4 2 0 –2 –4 –6 AVCC = 5V fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) –8 –10 0 2 4 6 8 10 12 14 TIME (µs) Figure 30. Output Current vs.
Data Sheet AD5757 DC-TO-DC BLOCK 90 80 AVCC = 4.5V AVCC = 5V AVCC = 5.5V 20mA 70 IOUT_x EFFICIENCY (%) VBOOST_x EFFICIENCY (%) 80 75 70 65 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 55 50 0 4 8 12 16 20 50 40 30 24 CURRENT (mA) 20 –40 09225-016 60 60 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET AVCC = 5V fSW = 410 kHz INDUCTOR = 10µH (XAL4040-103) –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 33. Efficiency at VBOOST_x vs.
AD5757 Data Sheet REFERENCE 5.0050 16 AVDD REFOUT TA = 25°C 14 5.0040 12 5.0035 REFOUT (V) 8 6 4 5.0030 5.0025 5.0020 5.0015 2 5.0010 0 0.2 0.4 0.6 0.8 1.0 1.2 TIME (ms) 5.0000 –40 09225-010 0 Figure 38. REFOUT Turn-On Transient –20 20 0 40 100 80 60 TEMPERATURE (°C) 09225-163 5.0005 –2 Figure 41. REFOUT vs. Temperature (When the AD5757 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is –4 mV.
Data Sheet AD5757 GENERAL 450 13.4 DVCC = 5V TA = 25°C 400 13.3 350 200 150 13.0 12.9 100 12.8 50 12.7 0 1 2 3 4 5 SDIN VOLTAGE (V) 12.6 –40 09225-007 0 DVCC = 5.5V –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 44. DICC vs. Logic Input Voltage Figure 46. Internal Oscillator Frequency vs. Temperature 8 14.4 7 14.2 6 FREQUENCY (MHz) 14.0 5 4 3 13.8 13.6 13.4 2 AIDD TA = 25°C IOUT = 0mA 1 0 10 15 20 25 VOLTAGE (V) 30 13.2 09225-009 CURRENT (mA) 13.1 13.
AD5757 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation, in LSBs, from the best fit line through the DAC transfer function. A typical INL vs. code plot is shown in Figure 8. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
Data Sheet AD5757 THEORY OF OPERATION The AD5757 is a quad, precision digital-to-current loop converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost, single-chip solution for generating current loop outputs. The current ranges available are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. The desired output configuration is user selectable via the DAC control register.
AD5757 Data Sheet TRANSFER FUNCTION For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA current output ranges, the output current is respectively expressed as 20 mA I OUT = N × D 2 24 mA IOUT = N × D 2 16 mA IOUT = N × D + 4 mA 2 where: D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. Rev.
Data Sheet AD5757 REGISTERS Table 6 shows an overview of the registers for the AD5757. Table 6. Data, Control, and Readback Registers for the AD5757 Register Data DAC Data Register (×4) Gain Register (×4) Offset Register (×4) Clear Code Register (×4) Control Main Control Register Software Register Slew Rate Control Register (×4) DAC Control Register (×4) DC-to-DC Control Register Readback Status Register Description Used to write a DAC code to each DAC channel. AD5757 data bits = D15 to D0.
AD5757 Data Sheet CHANGING AND REPROGRAMMING THE RANGE To correctly write to and set up the part from a power-on condition, use the following sequence: 1. 2. 3. 4. 5. Perform a hardware or software reset after initial power-on. The dc-to-dc converter supply block must be configured. Set the dc-to-dc switching frequency, maximum output voltage allowed, and the phase that the four dc-to-dc channels clock at. Configure the DAC control register on a per channel basis.
Data Sheet AD5757 DATA REGISTERS The input register is 24 bits wide. When PEC is enabled, the input register is 32 bits wide, with the last eight bits corresponding to the PEC code (see the Packet Error Checking section for more information on PEC). When writing to a data register, the format in Table 7 must be used. DAC Data Register When writing to the AD5757 DAC data registers, D15 to D0 are used for the DAC data bits.
AD5757 Data Sheet Gain Register Offset Register The 16-bit gain register, as shown in Table 10, allows the user to adjust the gain of each channel in steps of 1 LSB. This is done by setting the DREG[2:0] bits to 010. It is possible to write the same gain code to all four DAC channels at the same time by setting the DREG[2:0] bits to 011. The gain register coding is straight binary as shown in Table 11. The default code in the gain register is 0xFFFF.
Data Sheet AD5757 CONTROL REGISTERS Main Control Register When writing to a control register, the format shown in Table 15 must be used. See Table 8 for information on the configuration of Bit D23 to Bit D16. The control registers are addressed by setting the DREG[2:0] bits to 111 and then setting the CREG[2:0] bits to the appropriate decode address for that register, according to Table 16. These CREG bits select among the various control registers.
AD5757 Data Sheet DAC Control Register The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 19 and Table 20. Table 19. Programming DAC Control Register D15 0 1 D14 1 D13 0 D12 X1 D11 X1 D10 X1 D9 X1 D8 INT_ENABLE D7 CLR_EN D6 OUTEN D5 RSET D4 DC_DC D3 X1 D2 R2 D1 R1 D0 R0 X = don’t care. Table 20.
Data Sheet AD5757 Software Register The software register has three functions. It allows the user to perform a software reset to the part. It can be used to set the user toggle bit, D11, in the status register. It is also used as part of the watchdog feature when it is enabled. This feature is useful to ensure that communication has not been lost between the MCU and the AD5757 and that the datapath lines are working properly (that is, SDIN, SCLK, and SYNC).
AD5757 Data Sheet Slew Rate Control Register no operation command. The no operation command for DUT_AD[1:0] = 00 is 0x1CE000; for other DUT addresses, Bit D22 and Bit D21 are set accordingly. This register is used to program the slew rate control for the selected DAC channel. The slew rate control is enabled/ disabled and programmed on a per channel basis. See Table 25 and the Digital Slew Rate Control section for more information.
Data Sheet AD5757 Status Register register is set, the status register contents can be read back on the SDO pin during every write sequence. Alternatively, if the STATREAD bit is not set, the status register can be read using the normal readback operation. The status register is a read only register. This register contains any fault information as a well as a ramp active bit and a user toggle bit. When the STATREAD bit in the main control Table 28.
AD5757 Data Sheet DEVICE FEATURES OUTPUT FAULT The AD5757 is equipped with a FAULT pin, an active low opendrain output allowing several AD5757 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by any one of the following fault scenarios: • • • The voltage at IOUT_x attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage.
Data Sheet AD5757 is not received by the software register within the timeout period, the ALERT pin goes active. If the error check fails, the FAULT pin goes low and the PEC error bit in the status register is set. After reading the status register, FAULT returns high (assuming there are no other faults), and the PEC error bit is cleared automatically. It is not recommended to tie both AD1 and AD0 low as a short low on SDIN could possibly lead to a zero-scale update for DAC A.
AD5757 Data Sheet attenuated at the output. The recommended values are C1 = 22 nF, C2 = 47 nF. The following equation describes the slew rate as a function of the step size, the update clock frequency, and the LSB size: Digitally controlling the slew rate of the output is necessary to meet the analog rate of change requirements for HART.
Data Sheet AD5757 Table 33. Recommended DC-to-DC Components 29.6 Symbol LDCDC CDCDC DDCDC 29.5 Manufacturer Coilcraft® Murata NXP It is recommended to place a 10 Ω, 100 nF low-pass RC filter after CDCDC. This consumes a small amount of power but reduces the amount of ripple on the VBOOST_x supply. 0mA TO 24mA RANGE, 24mA OUTPUT OUTPUT UNLOADED 29.4 DC-to-DC Converter Operation 29.3 29.2 29.1 DC-DCMaxV = 29.5V DC-DCx BIT = 1 29.0 fSW = 410kHz 28.9 TA = 25°C 28.
AD5757 Data Sheet DC-to-DC Converter Compensation Capacitors AICC SUPPLY REQUIREMENTS—SLEWING As the dc-to-dc converter operates in DCM, the uncompensated transfer function is essentially a single-pole transfer function. The pole frequency of the transfer function is determined by the dc-to-dc converter’s output capacitance, input and output voltage, and output load. The AD5757 uses an external capacitor in conjunction with an internal 150 kΩ resistor to compensate the regulator loop.
Data Sheet 20 0.4 16 0.3 12 0.2 8 AICC IOUT VBOOST 0.1 0 0 0.5 1.0 4 1.5 TIME (ms) 2.0 2.5 0 0.5 16 0.3 12 0.2 8 0.1 4 0 AICC CURRENT (A) 0.6 28 24 0.5 20 0.4 16 0.3 12 0.2 8 0.1 4 0 0 0.5 1.0 1.5 TIME (ms) 2.0 0 2.5 3 TIME (ms) R2 5 6 0 The IGATE functionality works by holding the gate of the external PMOS transistor at (VBOOST_x − 5 V). This means that the majority of the channels power dissipation will take place in this external PMOS transistor.
AD5757 Data Sheet APPLICATIONS INFORMATION CURRENT OUTPUT MODE WITH INTERNAL RSET When using the internal RSET resistor in current output mode, the output is significantly affected by how many other channels using the internal RSET are enabled and by the dc crosstalk from these channels. The internal RSET specifications in Table 1 are for all channels enabled with the internal RSET selected and outputting the same code. For every channel enabled with the internal RSET, the offset error decreases.
Data Sheet AD5757 TRANSIENT VOLTAGE PROTECTION AD5757 The AD5757 contains ESD protection diodes that prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD5757 from excessively high voltage transients, external power diodes and a surge current limiting resistor (RP) are required, as shown in Figure 63. A typical value for RP is 10 Ω.
AD5757 Data Sheet DC-to-DC Converters GALVANICALLY ISOLATED INTERFACE To achieve high efficiency, good regulation, and stability, a welldesigned printed circuit board layout is required. In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur.
Data Sheet AD5757 INDUSTRIAL HART CAPABLE ANALOG OUTPUT APPLICATION adheres to the HART physical layer specifications as defined by the HART Communication Foundation. Many industrial control applications have requirements for accurately controlled current output signals, and the AD5757 is ideal for such applications. Figure 67 shows the AD5757 in a circuit design for a HART-enabled output module, specifically for use in an industrial control application.
AD5757 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.60 MAX 0.60 MAX 64 49 1 PIN 1 INDICATOR 48 PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 MIN 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-13-2012-C SEATING PLANE 16 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 17 BOTTOM VIEW TOP VIEW 1.00 0.85 0.
