Datasheet

Data Sheet AD5755-1
Rev. E | Page 9 of 52
TIMING CHARACTERISTICS
AV
DD
= V
BOOST_x
= 15 V; AV
SS
= −15 V; DV
DD
= 2.7 V to 5.5 V; AV
CC
= 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =
GNDSW
x
= 0 V; REFIN = 5 V; voltage outputs: R
L
= 1 kΩ, C
L
= 220 pF; current outputs: R
L
= 300 Ω; all specifications T
MIN
to T
MAX
, unless
otherwise noted.
Table 3.
Parameter
1, 2, 3
Limit at T
MIN
, T
MAX
Unit Description
t
1
33 ns min SCLK cycle time
t
2
13 ns min SCLK high time
t
3
13 ns min SCLK low time
t
4
13 ns min
SYNC
falling edge to SCLK falling edge setup time
t
5
13 ns min 24
th
/32
nd
SCLK falling edge to
SYNC
rising edge (see Figure 78)
t
6
198 ns min
SYNC
high time
t
7
5 ns min Data setup time
t
8
5 ns min Data hold time
t
9
20 µs min
SYNC
rising edge to
LDAC
falling edge (all DACs updated or any channel has
digital slew rate control enabled)
5 µs min
SYNC
rising edge to
LDAC
falling edge (single DAC updated)
t
10
10 ns min
LDAC
pulse width low
t
11
500 ns max
LDAC
falling edge to DAC output response time
t
12
See the AC Performance
Characteristics section
µs max DAC output settling time
t
13
10 ns min CLEAR high time
t
14
5 µs max CLEAR activation time
t
15
40 ns max SCLK rising edge to SDO valid
t
16
21 µs min
SYNC
rising edge to DAC output response time (
LDAC
= 0) (all DACs updated)
5 µs min
SYNC
rising edge to DAC output response time (
LDAC
= 0) (single DAC updated)
t
17
500
ns min
LDAC
falling edge to
SYNC
rising edge
t
18
800 ns min
RESET
pulse width
t
19
4
20 µs min
SYNC
high to next
SYNC
low (digital slew rate control enabled) (all DACs updated)
5 µs min
SYNC
high to next
SYNC
low (digital slew rate control disabled) (single DAC
updated)
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.2 V.
3
See Figure 3, Figure 4, Figure 5, and Figure 6.
4
This specification applies if
LDAC
is held low during the write cycle; otherwise, see t
9
.