Datasheet

Data Sheet AD5755-1
Rev. E | Page 33 of 52
DATA REGISTERS
The input register is 24 bits wide. When PEC is enabled, the
input register is 32 bits wide, with the last eight bits correspond-
ing to the PEC code (see the Packet Error Checking section for
more information on PEC). When writing to a data register, the
format in Table 8 must be used.
DAC Data Register
When writing to the AD5755-1 DAC data registers, D15 to D0
are used for DAC data bits. Table 10 shows the register format
and Table 9 describes the function of Bit D23 to Bit D16.
Table 8. Writing to a Data Register
MSB LSB
D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0
R/
W
DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 Data
Table 9. Input Register Decode
Bit Description
R/
W
Indicates a read from or a write to the addressed register.
DUT_AD1, DUT_AD0 Used in association with the external pins, AD1 and AD0, to determine which AD5755-1 device is being
addressed by the system controller. It is not recommended to tie both AD1 and AD0 low when using PEC, see
the Packet Error Checking section.
DUT_AD1 DUT_AD0 Function
0 0 Addresses part with Pin AD1 = 0, Pin AD0 = 0
0 1 Addresses part with Pin AD1 = 0, Pin AD0 = 1
1 0 Addresses part with Pin AD1 = 1, Pin AD0 = 0
1 1 Addresses part with Pin AD1 = 1, Pin AD0 = 1
DREG2, DREG1, DREG0
Selects whether a data register or a control register is written to. If a control register is selected, a further decode
of CREG bits (see Table 17) is required to select the particular control register, as follows.
DREG2 DREG1 DREG0 Function
0 0 0 Write to DAC data register (individual channel write)
0 1 0 Write to gain register
0 1 1 Write to gain register (all DACs)
1 0 0 Write to offset register
1 0 1 Write to offset register (all DACs)
1 1 0 Write to clear code register
1 1 1 Write to a control register
DAC_AD1, DAC_AD0 These bits are used to decode the DAC channel.
DAC_AD1 DAC_AD0 DAC Channel/Register Address
0 0 DAC A
0 1 DAC B
1 0 DAC C
1 1 DAC D
X X These are don’t cares if they are not relevant to the operation being performed.
Table 10. Programming the DAC Data Registers
MSB LSB
D23
D22
D21
D20
D19
D18
D17
D16
D15 to D0
R/
W
DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 DAC data