Datasheet
Data Sheet AD5755-1
Rev. E | Page 13 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
POC
RESET
AV
DD
COMP
LV_A
CHARTA
+V
SENSE_A
COMP
DCDC_A
V
BOOST_A
V
OUT_A
I
OUT_A
AV
SS
COMP
LV_B
CHARTB
+V
SENSE_B
V
OUT_B
COMP
DCDC_B
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
R
SET_C
R
SET_D
REFOUT
REFIN
COMP
LV_D
CHARTD
+V
SENSE_D
COMP
DCDC_D
V
BOOST_D
V
OUT_D
I
OUT_D
AV
SS
COMP
LV_C
CHARTC
+V
SENSE_C
V
OUT_C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R
SET_B
R
SET_A
REFGND
REFGND
AD0
AD1
SYNC
SCLK
SDIN
SDO
DV
DD
DGND
LDAC
CLEAR
ALERT
FAULT
COMP
DCDC_C
I
OUT_C
V
BOOST_C
AV
CC
SW
C
GNDSW
C
GNDSW
D
SW
D
AV
SS
SW
A
GNDSW
A
GNDSW
B
SW
B
AGND
V
BOOST_B
I
OUT_B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD5755-1
TOP VIEW
(Not to Scale)
09266-006
PIN 1
INDICATOR
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED TO THE POTENTIAL OF
THE AV
SS
PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY
UNCONNECTED. IT IS RECOMMENDED THAT THE PAD BE THERMALLY
CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.
Figure 7. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 R
SET_B
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I
OUT_B
temperature drift performance. See the Device Features section.
2 R
SET_A
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I
OUT_A
temperature drift performance. See the Device Features section.
3, 4 REFGND Ground Reference Point for Internal Reference.
5 AD0 Address Decode for the Device Under Test (DUT) on the Board.
6 AD1
Address Decode for the DUT on the Board. It is not recommended to tie both AD1 and AD0 low when using PEC,
see the Packet Error Checking section.
7
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
8 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This operates at clock
speeds of up to 30 MHz.
9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK.
10 SDO Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 4 and Figure 5.
11 DV
DD
Digital Supply. The voltage range is from 2.7 V to 5.5 V.
12 DGND Digital Ground.
13
LDAC
Load DAC, Active Low Input. This is used to update the DAC register and consequently the DAC outputs. When
tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held
high during the write cycle, the DAC input register is updated, but the DAC output update only takes place at
the falling edge of LDAC
(see Figure 3). Using this mode, all analog outputs can be updated simultaneously. The
LDAC
pin must not be left unconnected.
14 CLEAR
Active High, Edge Sensitive Input. Asserting this pin sets the output current and voltage to the preprogrammed
clear code bit setting. Only channels enabled to be cleared are cleared. See the Device Features section for more
information. When CLEAR is active, the DAC output register cannot be written to.