Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA and Voltage Output DAC, Dynamic Power Control, HART Connectivity AD5755-1 Data Sheet in current mode. This is achieved by regulating the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5755-1.
AD5755-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Device Features ............................................................................... 40 Applications ....................................................................................... 1 Output Fault ................................................................................ 40 General Description ...........................................
Data Sheet AD5755-1 REVISION HISTORY 11/12—Rev. D to Rev. E Changes to Figure 2........................................................................... 4 Changed Thermal Impedance from 20°C/W to 28°C/W ..........12 Changes to Pin 6 Description ........................................................13 Changes to Pin 27 Description ......................................................14 Changes to Figure 26 ......................................................................
AD5755-1 Data Sheet DETAILED FUNCTIONAL BLOCK DIAGRAM AV CC 5.0V AV SS –15V/0V AGND DVDD DGND LDAC CLEAR SCLK SDIN SYNC SDO INPUT SHIFT REGISTER AND CONTROL STATUS REGISTER REFOUT REFIN SWA POWER-ON RESET FAULT ALERT AV DD +15V VBOOST_A DC-TO-DC CONVERTER POWER CONTROL 16 INPUT REG A DAC REG A 16 7.4V TO 29.
Data Sheet AD5755-1 SPECIFICATIONS AVDD = VBOOST_x = 15 V; AVSS = −15 V/0 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
AD5755-1 Parameter1 CURRENT OUTPUT Output Current Ranges Resolution ACCURACY (EXTERNAL RSET) Total Unadjusted Error (TUE) TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Drift2 Gain Error Gain TC2 Full-Scale Error Full-Scale TC2 DC Crosstalk ACCURACY (INTERNAL RSET) Total Unadjusted Error (TUE)4, 5 TUE Long-Term Stability Relative Accuracy (INL) Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error4, 5 Offset Error Drift2 Gain Error G
Data Sheet Parameter1 REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage DC Input Impedance Reference Output Output Voltage Reference TC2 Output Noise (0.1 Hz to 10 Hz)2 Noise Spectral Density2 Output Voltage Drift vs.
AD5755-1 Parameter1 AIDD AISS Data Sheet Min −11 Typ 8.6 Max 10.5 Unit mA 7 −8.8 7.5 mA mA 9.2 11 mA mA 1 2.7 mA mA 1 mA mW −1.
Data Sheet AD5755-1 TIMING CHARACTERISTICS AVDD = VBOOST_x = 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
AD5755-1 Data Sheet Timing Diagrams t1 SCLK 1 2 24 t3 t6 t2 t4 t5 SYNC t8 t7 SDIN t19 MSB LSB t10 t10 t9 LDAC t17 t12 t11 VOUT_x LDAC = 0 t12 t16 VOUT_x t13 CLEAR t14 VOUT_x 09226-002 t18 RESET Figure 3. Serial Interface Timing Diagram SCLK 1 1 24 24 t6 SYNC MSB LSB MSB LSB INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION MSB SDO LSB UNDEFINED t15 Figure 4. Readback Timing Diagram Rev.
Data Sheet LSB 1 AD5755-1 MSB 16 2 SCLK SDO R/W DUT_ AD1 DUT_ AD0 SDO DISABLED X X X D15 D14 D1 D0 SDO_ ENAB STATUS STATUS STATUS STATUS Figure 5. Status Readback During Write 200µA TO OUTPUT PIN IOL VOH (MIN) OR VOL (MAX) CL 50pF 200µA IOH Figure 6. Load Circuit for SDO Timing Diagram Rev.
AD5755-1 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4.
Data Sheet AD5755-1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RSET_C RSET_D REFOUT REFIN COMPLV_D CHARTD +VSENSE_D COMPDCDC_D VBOOST_D VOUT_D IOUT_D AVSS COMPLV_C CHARTC +VSENSE_C VOUT_C PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD5755-1 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COMPDCDC_C IOUT_C VBOOST_C AVCC SWC GNDSWC GNDSWD SWD AVSS SWA GNDSWA GNDSWB SWB AGND VBOOST_B IOUT_B NOTES 1.
AD5755-1 Pin No. 15 Mnemonic ALERT 16 FAULT 17 POC 18 19 20 RESET AVDD COMPLV_A 21 22 23 CHARTA +VSENSE_A COMPDCDC_A 24 VBOOST_A 25 26 27 28 VOUT_A IOUT_A AVSS COMPLV_B 29 30 31 32 CHARTB +VSENSE_B VOUT_B COMPDCDC_B 33 34 IOUT_B VBOOST_B 35 36 AGND SWB 37 38 39 GNDSWB GNDSWA SWA 40 AVSS 41 SWD 42 43 44 GNDSWD GNDSWC SWC 45 AVCC Data Sheet Description Active High Output. This pin is asserted when there has been no SPI activity on the interface pins for a predetermined time.
Data Sheet Pin No. 46 Mnemonic VBOOST_C 47 48 IOUT_C COMPDCDC_C 49 50 51 52 VOUT_C +VSENSE_C CHARTC COMPLV_C 53 54 55 56 AVSS IOUT_D VOUT_D VBOOST_D 57 COMPDCDC_D 58 59 60 +VSENSE_D CHARTD COMPLV_D 61 62 REFIN REFOUT 63 RSET_D 64 RSET_C EPAD AD5755-1 Description Supply for Channel C Current Output Stage (see Figure 73). This is also the supply for the VOUT_x stage, which is regulated to 15 V by the dc-to-dc converter.
AD5755-1 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUTS 0.0015 0.0015 ±10V RANGE AVDD = +15V ±5V RANGE AVSS = –15V +10V RANGE TA = 25°C +5V RANGE +10V RANGE WITH DCDC 0.0010 INL ERROR (%FSR) 0.0005 0 –0.0005 0.0005 0 10k 20k 30k 40k 50k 60k CODE 09226-127 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 8. Integral Nonlinearity Error vs. DAC Code Figure 11. Integral Nonlinearity Error vs. Temperature 1.0 1.
Data Sheet AD5755-1 0.0025 0.0020 –0.010 +5V RANGE +12V RANGE AVDD = +15V AVSS = 0V OUTPUT UNLOADED –0.015 –0.020 –0.025 –0.030 –20 0 20 40 60 80 0.0010 0.0005 0 ±5V RANGE ±10V RANGE –0.0005 –0.0010 AVDD = +15V AVSS = –15V OUTPUT UNLOADED –0.0015 –0.0020 –40 100 –20 0 TEMPERATURE (°C) Figure 14. Total Unadjusted Error vs. Temperature, Single Supply GAIN ERROR (%FSR) 0.004 0.002 0 100 AVDD = +15V AVSS = –15V OUTPUT UNLOADED 0.004 0.002 0 –0.002 –0.002 –20 0 20 40 60 80 –0.
AD5755-1 Data Sheet 0.0020 0.0015 0.0015 OUTPUT VOLTAGE DELTA (V) 0.0020 0.0005 0V TO 10V RANGE MAX INL 0V TO 10V RANGE MIN INL TA = 25°C AVSS = –26.4V FOR AVDD > +26.4V 0 –0.0005 –0.0010 0.0010 0.0005 0 –0.0005 –0.0010 –0.0015 –0.0015 10 15 20 25 –0.0020 –20 09226-034 –0.0020 30 SUPPLY (V) 0.4 8 0.2 0 –8 –4 0 4 8 12 16 20 12 AVDD = +15V AVSS = –15V ALL RANGES TA = 25°C AVSS = –26.4V FOR AVDD > +26.4V OUTPUT VOLTAGE (V) 0.6 –12 Figure 23.
Data Sheet AD5755-1 20 15 OUTPUT VOLTAGE (mV) 10 5 0 –5 –10 10 5 0 –5 –10 –15 AVDD = +15V AVSS = –15V TA = 25°C –15 –20 THE EXTERNAL RESISTOR IS A VISHAY S102C, 0.6ppm RESISTOR 1 2 3 4 5 TIME (µs) –25 0 100 40 20 5 0 –5 0 –20 –40 –60 POC = 1 POC = 0 –80 AVDD = +15V AVSS = –15V ±10V RANGE TA = 25°C INT_ENABLE = 1 –100 –10 1 2 3 4 5 6 7 8 9 10 TIME (s) 09226-040 –120 –15 0 –140 0 AVDD = +15V AVSS = –15V 4 6 8 10 Figure 30. VOUT_x vs.
AD5755-1 Data Sheet CURRENT OUTPUTS 0.0010 0.0025 AVDD = +15V AVSS = –15V TA = 25°C 0.0008 0.0006 INL ERROR (%FSR) 0.0004 0.0005 –0.0005 4mA TO 4mA TO 4mA TO 4mA TO 20mA, 20mA, 20mA, 20mA, 10000 20000 30000 40000 50000 –0.0002 20mA RANGE MAX INL 24mA RANGE MAX INL 20mA RANGE MIN INL 20mA RANGE MAX INL 20mA RANGE MAX INL 24mA RANGE MIN INL AVDD = +15V AVSS = –15V/0V –0.0004 –0.
Data Sheet AD5755-1 0.02 0.03 0.01 0.01 0 –0.01 AVDD = +15V AVSS = –15V/0V –0.02 –0.03 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO –0.04 –0.05 –0.06 –0.07 –0.08 –40 –20 0 20mA INTERNAL RSET 20mA INTERNAL RSET 24mA INTERNAL RSET 20mA EXTERNAL RSET 20mA EXTERNAL RSET 24mA EXTERNAL RSET 20 40 60 TEMPERATURE (°C) –0.01 –0.02 AVDD = +15V AVSS = –15V/0V –0.03 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO –0.04 –0.05 80 –0.06 –40 100 Figure 38. Total Unadjusted Error vs. Temperature 0.03 0.0025 0.
AD5755-1 Data Sheet 1.0 6 ALL RANGES INTERNAL AND EXTERNAL RSET TA = 25°C AVSS = –26.4V FOR AVDD > +26.4V 0.8 0.4 4 CURRENT (µA) DNL ERROR (LSB) 0.6 AVDD = +15V AVSS = –15V TA = 25°C RLOAD = 300Ω 5 0.2 DNL ERROR MAX DNL ERROR MIN 0 –0.2 3 2 –0.4 –0.6 1 –0.8 20 25 30 SUPPLY (V) 0 0 10 15 20 TIME (µs) Figure 47. Output Current vs. Time on Power-Up Figure 44. Differential Nonlinearity Error vs. AVDD 0.012 4 2 0.010 0 CURRENT (µA) 0.008 0.006 –2 –4 0.
Data Sheet AD5755-1 8 30 0mA TO 24mA RANGE 1kΩ LOAD FSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 7 HEADROOM VOLTAGE (V) 20 IOUT, TA = –40°C IOUT, TA = +25°C IOUT, TA = +105°C 10 0 –0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 5 4 3 2 1 0 0 1.75 5 10 0 25 –20 20 –40 IOUT_x PSRR (dB) 30 IOUT, AVCC = 4.5V IOUT, AVCC = 5.0V IOUT, AVCC = 5.5V 10 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 5 0 –0.25 0 0.25 0.50 0.75 1.00 1.25 1.
AD5755-1 Data Sheet DC-TO-DC BLOCK 80 90 70 IOUT_x EFFICIENCY (%) 80 75 70 65 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 55 50 0 4 8 12 16 20 50 40 30 24 CURRENT (mA) 20 –40 09226-016 60 60 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET AVCC = 5V fSW = 410 kHz INDUCTOR = 10µH (XAL4040-103) –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 55. Efficiency at VBOOST_x vs.
Data Sheet AD5755-1 REFERENCE 5.0050 16 AVDD REFOUT TA = 25°C 14 5.0040 12 5.0035 REFOUT (V) 8 6 4 5.0030 5.0025 5.0020 5.0015 2 5.0010 0 0.2 0.4 0.6 0.8 1.0 1.2 TIME (ms) 5.0000 –40 09226-010 0 Figure 60. REFOUT Turn-On Transient –20 0 20 40 60 80 100 TEMPERATURE (°C) 09226-163 5.0005 –2 Figure 63. REFOUT vs. Temperature (When the AD5755-1 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is −4 mV.
AD5755-1 Data Sheet GENERAL 13.4 450 DVCC = 5V TA = 25°C 400 13.3 350 FREQUENCY (MHz) 13.2 250 200 150 13.1 13.0 12.9 12.8 100 12.7 50 0 1 2 3 4 5 SDIN VOLTAGE (V) 12.6 –40 09226-007 0 DVCC = 5.5V –20 0 20 40 60 80 09226-020 DICC (µA) 300 100 TEMPERATURE (°C) Figure 66. DICC vs. Logic Input Voltage Figure 69. Internal Oscillator Frequency vs. Temperature 10 14.4 8 14.2 6 AIDD AISS TA = 25°C VOUT = 0V OUTPUT UNLOADED 2 0 14.0 FREQUENCY (MHz) –2 –4 13.8 13.6 13.
Data Sheet AD5755-1 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation, in LSBs, from the best fit line through the DAC transfer function. A typical INL vs. code plot is shown in Figure 8. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
AD5755-1 Data Sheet Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition (~0x7FFF to 0x8000). See Figure 26.
Data Sheet AD5755-1 THEORY OF OPERATION The AD5755-1 is a quad, precision digital-to-current loop and voltage output converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost, single-chip solution for generating current loop and unipolar/bipolar voltage outputs. The current ranges available are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. The voltage ranges available are 0 V to 5 V, ±5 V, 0 V to 10 V, and ±10 V.
AD5755-1 Data Sheet with all zeros. This means that if the user clears the part after power-up, the output is actively driven to 0 V (if the channel has been enabled for clear). OUTPUT I/V AMPLIFIER VREFIN After a device power on, or a device reset, it is recommended to wait 100 μs or more before writing to the device to allow time for internal calibrations to take place. LDAC SERIAL INTERFACE SCLK SYNC SDIN In this mode, LDAC is held low while data is being clocked into the DAC data register.
Data Sheet AD5755-1 REGISTERS Table 7 shows an overview of the registers for the AD5755-1. Table 7. Data, Control, and Readback Registers for the AD5755-1 Register Data DAC Data Register (×4) Gain Register (×4) Offset Register (×4) Clear Code Register (×4) Control Main Control Register Software Register Slew Rate Control Register (×4) DAC Control Register (×4) DC-to-DC Control Register Readback Status Register Description Used to write a DAC code to each DAC channel. AD5755-1 data bits = D15 to D0.
AD5755-1 Data Sheet PROGRAMMING SEQUENCE TO WRITE/ENABLE THE OUTPUT CORRECTLY CHANGING AND REPROGRAMMING THE RANGE To correctly write to and set up the part from a power-on condition, use the following sequence: 1. 2. 3. 4. 5. Perform a hardware or software reset after initial power-on. The dc-to-dc converter supply block must be configured. Set the dc-to-dc switching frequency, maximum output voltage allowed, and the phase that the four dc-to-dc channels clock at.
Data Sheet AD5755-1 DATA REGISTERS The input register is 24 bits wide. When PEC is enabled, the input register is 32 bits wide, with the last eight bits corresponding to the PEC code (see the Packet Error Checking section for more information on PEC). When writing to a data register, the format in Table 8 must be used. DAC Data Register When writing to the AD5755-1 DAC data registers, D15 to D0 are used for DAC data bits.
AD5755-1 Data Sheet Gain Register in steps of 1 LSB. This is done by setting the DREG[2:0] bits to 100. It is possible to write the same offset code to all four DAC channels at the same time by setting the DREG[2:0] bits to 101. The offset register coding is straight binary as shown in Table 14. The default code in the offset register is 0x8000, which results in zero offset programmed to the output. See the Digital Offset and Gain Control section for more information.
Data Sheet AD5755-1 CONTROL REGISTERS Main Control Register When writing to a control register, the format shown in Table 16 must be used. See Table 9 for information on the configuration of Bit D23 to Bit D16. The control registers are addressed by setting the DREG[2:0] bits to 111 and then setting the CREG[2:0] bits to the appropriate decode address for that register, according to Table 17. These CREG bits select among the various control registers.
AD5755-1 Data Sheet DAC Control Register The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 20 and Table 21. Table 20. Programming DAC Control Register D15 0 1 D14 1 D13 0 D12 X1 D11 X1 D10 X1 D9 X1 D8 INT_ENABLE D7 CLR_EN D6 OUTEN D5 RSET D4 DC_DC D3 OVRNG D2 R2 D1 R1 D0 R0 X = don’t care. Table 21.
Data Sheet AD5755-1 Software Register The software register has three functions. It allows the user to perform a software reset to the part. It can be used to set the user toggle bit, D11, in the status register. It is also used as part of the watchdog feature when it is enabled. This feature is useful to ensure that communication has not been lost between the MCU and the AD5755-1 and that the datapath lines are working properly (that is, SDIN, SCLK, and SYNC).
AD5755-1 Data Sheet Slew Rate Control Register This register is used to program the slew rate control for the selected DAC channel. This feature is available on both the current and voltage outputs. The slew rate control is enabled/ disabled and programmed on a per channel basis. See Table 26 and the Digital Slew Rate Control section for more information. READBACK OPERATION Readback mode is invoked by setting the R/W bit = 1 in the serial input register write.
Data Sheet AD5755-1 Status Register The status register is a read only register. This register contains any fault information as a well as a ramp active bit and a user toggle bit. When the STATREAD bit in the main control register is set, the status register contents can be read back on the SDO pin during every write sequence. Alternatively, if the STATREAD bit is not set, the status register can be read using the normal readback operation. Table 29.
AD5755-1 Data Sheet DEVICE FEATURES OUTPUT FAULT The AD5755-1 is equipped with a FAULT pin, an active low open-drain output allowing several AD5755-1 devices to be connected together to one pull-up resistor for global fault detection.
Data Sheet AD5755-1 ASYNCHRONOUS CLEAR values returned during the status readback during a write operation should be ignored. If status readback during a write is disabled, the user can still use the normal readback operation to monitor status register activity with PEC. CLEAR is an active high, edge-sensitive input that allows the output to be cleared to a preprogrammed 16-bit code. This code is user programmable via a per channel 16-bit clear code register.
AD5755-1 Data Sheet directly to the gain/TUE error of the AD5755-1 with the external RSET resistor, shown in Table 1 (expressed in % FSR). HART The AD5755-1 has four CHART pins, one corresponding to each output channels. A HART signal can be coupled into these pins. The HART signal appears on the corresponding current output, if the output is enabled. Table 31 shows the recommended input voltages for the HART signal at the CHART pin.
Data Sheet AD5755-1 POWER DISSIPATION CONTROL The AD5755-1 contains integrated dynamic power control using a dc-to-dc boost converter circuit, allowing reductions in power consumption from standard designs when using the part in current output mode. In standard current input module designs, the load resistor values can range from typically 50 Ω to 750 Ω. Output module systems must source enough voltage to meet the compliance voltage requirement across the full range of load resistor values.
AD5755-1 Data Sheet current and small load resistor), the dc-to-dc converter enters a pulse-skipping mode to minimize switching power dissipation. DC-to-DC Converter Inductor Selection For typical 4 mA to 20 mA applications, a 10 µH inductor (such as the XAL4040-103 from Coilcraft), combined with a switching frequency of 410 kHz, allows up to 24 mA to be driven into a load resistance of up to 1 kΩ with an AVCC supply of 4.5 V to 5.5 V.
Data Sheet AD5755-1 0.8 0.4 16 0.3 12 0.2 8 AICC IOUT VBOOST 0.1 4 0 0 0 0.5 1.0 1.5 TIME (ms) 2.0 2.5 Figure 83. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load with External 51 kΩ Compensation Resistor 16 0.3 12 0.2 8 0.1 4 0.5 1.0 1.5 TIME (ms) 2.0 0 2.5 Figure 84. AICC Current vs. Time for 24 mA Step Through 500 Ω Load with External 51 kΩ Compensation Resistor Using slew rate control can greatly reduce the AVCC supplies current requirements, as shown in Figure 85.
AD5755-1 Data Sheet APPLICATIONS INFORMATION VOLTAGE AND CURRENT OUTPUT RANGES ON THE SAME TERMINAL When using a channel of the AD5755-1, the current and voltage output pins can be connected to two separate terminals or tied together and connected to a single terminal. There is no conflict with tying the two output pins together because only the voltage output or the current output can be enabled at any one time.
Data Sheet AD5755-1 DRIVING INDUCTIVE LOADS MICROPROCESSOR INTERFACING When driving inductive or poorly defined loads, a capacitor may be required between IOUT_x and AGND to ensure stability. A 0.01 µF capacitor between IOUT_x and AGND ensures stability of a load of 50 mH. The capacitive component of the load may cause slower settling, although this may be masked by the settling time of the AD5755-1. There is no maximum capacitance limit for the current output of the AD5755-1.
AD5755-1 Data Sheet Traces GALVANICALLY ISOLATED INTERFACE The power supply lines of the AD5755-1 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to prevent radiating noise to other parts of the board and should never be run near the reference inputs.
Data Sheet AD5755-1 INDUSTRIAL HART CAPABLE ANALOG OUTPUT APPLICATION—SHARED VOUT_X AND IOUT_X PIN CHARTx pin of the AD5755-1. Such a configuration results in the AD5700 HART modem output modulating the 4 mA to 20 mA analog current without affecting the dc level of the current. This circuit adheres to the HART physical layer specifications as defined by the HART Communication Foundation.
AD5755-1 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.60 MAX 0.60 MAX 64 49 1 PIN 1 INDICATOR 48 PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-13-2012-C SEATING PLANE 16 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 17 BOTTOM VIEW TOP VIEW 1.00 0.
Data Sheet AD5755-1 NOTES Rev.
AD5755-1 Data Sheet NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09226-0-11/12(E) Rev.