Datasheet

AD5751 Data Sheet
Rev. B | Page 6 of 32
Parameter
1
Min Typ Max Unit Test Conditions/Comments
Gain TC
4
±1 ppm FSR/°C
Full-Scale Error −0.1 +0.1 % FSR
−0.07 ±0.02 +0.07 % FSR T
A
= 25°C
Full-Scale TC
4
±2 ppm FSR/°C
OUTPUT CHARACTERISTICS
4
Current Loop Compliance Voltage 0 AV
DD
− 2.75 V
Resistive Load Chosen such that compliance is not
exceeded
Inductive Load See test conditions/comments column H Needs appropriate capacitor at higher
inductance values; see Driving Inductive
Loads section
Settling Time
4 mA to 20 mA, Full-Scale Step 8.5 µs 250 Ω load
120 µA Step, 4 mA to 20 mA Range 1.2 µs 250 Ω load
DC PSRR 1 µA/V
Output Impedance 130 MΩ
DIGITAL INPUTS
4
JEDEC compliant
Input High Voltage, V
IH
2 V
Input Low Voltage, V
IL
0.8 V
Input Current −1 +1 µA Per pin
Pin Capacitance 5 pF Per pin
DIGITAL OUTPUTS
4
FAULT, IFAULT, TEMP, VFAULT
V
OL
, Output Low Voltage 0.4 V 10 kΩ pull-up resistor to DVCC
0.6 V At 2.5 mA
V
OH
, Output High Voltage 3.6 V 10 kΩ pull-up resistor to DVCC
SDO
V
OL
, Output Low Voltage 0.5 0.5 V Sinking 200 µA
V
OH
, Output High Voltage DVCC − 0.5 DVCC − 0.5 V Sourcing 200 µA
High Impedance Output
Capacitance
3 pF
High Impedance Leakage Current −1 +1 µA
POWER REQUIREMENTS
AV
DD
10.8 55 V
DV
CC
Input Voltage 2.7 5.5 V
AI
DD
4.4 5.6 mA Output unloaded, output disabled
5.2 6.2 mA Current output enabled
5.2
6.2
mA
Voltage output enabled
DI
CC
0.3 1 mA V
IH
= DVCC, V
IL
= GND
Power Dissipation 108 mW AVDD = 24 V, outputs unloaded
1
Temperature range: −40°C to +105°C; typical at +25°C.
2
Overranges are nominal; gain and offset are not trimmed as per nominal ranges.
3
Specification includes gain and offset errors, over temperature, and drift after 1000 hours, T
A
= 125°C.
4
Guaranteed by characterization, but not production tested.