Datasheet

AD5751 Data Sheet
Rev. B | Page 28 of 32
PROGRAMMABLE OVERRANGE MODES
The AD5751 contains an overrange mode for most of the
available ranges. The overranges are selected by configuring the
R3, R1, R1, and R0 bits (or pins) accordingly.
In voltage mode, depending on selected range, the overranges
are 10% or 20%, providing programmable output ranges of 0 V
to 6 V, 0 V to 12 V, and 0 V to 44 V. The 0 V to 4.096 V analog
input remains the same.
In current mode, the overranges are typically 2%. In current
mode, the overrange capability is only available on three ranges,
0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. For these
ranges, the analog input also remains the same (0 V to 4.096 V).
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy
environments, the AD5751 offers the option of error checking
based on an 8-bit (CRC-8) cyclic redundancy check. The device
controlling the AD5751 should generate an 8-bit frame check
sequence using the following polynomial:
C(x) = x
8
+ x
2
+ x
1
+ 1
This is added to the end of the data-word, and 24 data bits are
sent to the AD5751 before taking
SYNC
high. If the AD5751
receives a 24-bit data frame, it performs the error check when
SYNC
goes high. If the check is valid, then the data is written to
the selected register. If the error check fails, the FAULT pin goes
low and Bit D3 of the status register is set. After reading this
register, this error flag is cleared automatically and the FAULT
pin goes high again.
SCLK
SDIN
SYNC
UPDATE ON SYNC HIGH
D15
(MSB)
D0
(LSB)
16-BIT DATA
16-BIT DATA TRANSER—NO ERROR CHECKING
SCLK
SDIN
SYNC
FAULT
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
FAULT GOES LOW IF
ERROR CHECK FAILS
D23
(MSB)
D8
(LSB) D7 D0
16-BIT DATA 8-BIT FCS
16-BIT DATA TRANSER WITH ERROR CHECKING
07269-010
Figure 54. PEC Error Checking Timing