Datasheet

AD5751 Data Sheet
Rev. B | Page 14 of 32
12
10
8
6
4
2
0
2722171272–3–8
VOLTAGE (V)
TIME (µs)
07269-026
Figure 17. Full-Scale Negative Step, 10 V Range
40
35
30
25
20
15
10
5
0
–5
2.52.01.51.00.50–0.5–1.0
V
OUT
(mV)
TIME (ms)
07269-027
Figure 18. V
OUT
vs. Time on Power-Up, Load = 2 kΩ || 200 pF
CH1
5.00V CH2 20.0mV
B
W
M1.0µs A CH1 3.00V
1
2
07269-028
Figure 19. V
OUT
Enable Glitch, Load = 2 kΩ || 1 nF
5µV/DIV 1s/DIV
07269-029
Figure 20. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)
100µV/DIV
1s/DIV
07269-030
Figure 21. Peak-to-Peak Noise (100 kHz Bandwidth)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
–0.2
2.01.5
V
DD
V
OUT
1.00.50–0.5–1.0–1.5
V
DD
(V)
V
OUT
(V)
TIME (ms)
07269-031
Figure 22. V
DD
and V
OUT
vs. Time on Power-Up