with V = +15 V or +12 V, V AD574A–SPECIFICATIONS (@unless+258Cotherwise noted) CC Model AD574AJ Typ Max AD574AK Typ Max Max Units 12 12 Bits LINEARITY ERROR @ +25°C TMIN to TMAX ±1 ±1 ± 1/2 ± 1/2 ± 1/2 ± 1/2 LSB LSB 12 Min AD574AL Typ 12 11 Min = +5 V, VEE = –15 V or –12 V RESOLUTION DIFFERENTIAL LINEARITY ERROR (Minimum Resolution for Which No Missing Codes are Guaranteed) TMIN to TMAX Min LOGIC 12 Bits UNIPOLAR OFFSET (Adjustable to Zero) ±2 ±1 ±1 LSB BIPOLAR OFFSET (Adju
AD574A Model Min AD574AS Typ Max Min AD574AT Typ Max Min AD574AU Typ Max Units RESOLUTION 12 12 12 Bits LINEARITY ERROR @ +25°C TMIN to TMAX ±1 ±1 ± 1/2 ±1 ± 1/2 ±1 LSB LSB DIFFERENTIAL LINEARITY ERROR (Minimum Resolution for Which No Missing Codes are Guaranteed) TMIN to TMAX 11 12 12 Bits UNIPOLAR OFFSET (Adjustable to Zero) ±2 ±1 ±1 LSB BIPOLAR OFFSET (Adjustable to Zero) ±4 ±4 ±2 LSB 0.
AD574A +5V SUPPLY VLOGIC DATA MODE SELECT 12/8 CHIP SELECT CS BYTE ADDRESS/ SHORT CYCLE AO READ/CONVERT R/C CHIP ENABLE CE +12/+15V SUPPLY VCC +10V REFERENCE REF OUT ANALOG COMMON AC REFERENCE INPUT REF IN -12/-15V SUPPLY VEE BIPOLAR OFFSET BIP OFF 10V SPAN INPUT 10VIN 1 STATUS STS DB11 27 MSB 28 MSB 2 CONTROL 3 3 4 5 SAR CLOCK 6 12 3k 7 COMP 12 10V REF 8 9 10 19.95k IDAC IDAC = 4 x N x IREF 8k IREF 11 12 9.
AD574A THE AD574A OFFERS GUARANTEED MAXIMUM LINEARITY ERROR OVER THE FULL OPERATING TEMPERATURE RANGE DEFINITIONS OF SPECIFICATIONS QUANTIZATION UNCERTAINTY LINEARITY ERROR Linearity error refers to the deviation of each individual code from a line drawn from “zero” through “full scale”. The point used as “zero” occurs 1/2 LSB (1.22 mV for 10 volt span) before the first code transition (all zeros to only the LSB “on”).
AD574A CIRCUIT OPERATION DRIVING THE AD574 ANALOG INPUT The AD574A is a complete 12-bit A/D converter which requires no external components to provide the complete successiveapproximation analog-to-digital conversion function. A block diagram of the AD574A is shown in Figure 1. The internal circuitry of the AD574 dictates that its analog input be driven by a low source impedance.
AD574A +VS TO A1 VREF A –VS TO A1 AGND + + C2 2 12/8 +VS 9 R2 100Ω 8 10k 10k GAIN +15V 100pF A1 AD585 1 2 3 4 5 6 R1 100k OFFSET 7 –VS ANALOG INPUT 0V TO +10V CONVERT C3 –15V 11 1 14 13 12 11 10 page. Analog input connections and calibration are easily accomplished; the unipolar operating mode is shown in Figure 4.
AD574A The full-scale trim is done by applying a signal 1 1/2 LSB below the nominal full scale (9.9963 for a 10 V range). Trim R2 to give the last transition (1111 1111 1110 to 1111 1111 1111). START CONVERT BIPOLAR OPERATION STATUS The connections for bipolar ranges are shown in Figure 5. Again, as for the unipolar ranges, if the offset and gain specifications are sufficient, one or both of the trimmers shown can be replaced by a 50 Ω ± 1% fixed resistor.
AD574A Figure 7 shows a complete timing diagram for the AD574A convert start operation. R/C should be low before both CE and CS are asserted; if R/C is high, a read operation will momentarily occur, possibly resulting in system bus contention. Either CE or CS may be used to initiate a conversion; however, use of CE is recommended since it includes one less propagation delay than CS and is the faster input. In Figure 7, CE is used to initiate the conversion. Table III.
AD574A GENERAL A/D CONVERTER INTERFACE CONSIDERATIONS to valid logic levels after the conversion cycle is completed. The STS line goes high 600 ns after R/C goes low and returns low 300 ns after data is valid. If conversion is initiated by a high pulse as shown in Figure 12, the data lines are enabled during the time when R/C is high. The falling edge of R/C starts the next conversion, and the data lines return to three-state (and remain three-state) until the next high pulse of R/C. Figure 12.
AD574A Note: Due to the large number of options that may be installed in the PC, the I/O bus loading should be limited to one Schottky TTL load. Therefore, a buffer/driver should be used when interfacing more than two AD574As to the I/O bus. 8086 Interface The data mode select pin (12/8) of the AD574A should be connected to VLOGIC to provide a 12-bit data output. To prevent possible bus contention, a demultiplexed and buffered address/ data bus is recommended.
AD574A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Plastic DIP Package (N-28A) C704d–10–8/88 28-Pin Ceramic DIP Package (D-28) 28-Terminal PLCC Package (P-28A) 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 4 5 PIN 1 IDENTIFIER 26 25 0.020 (0.50) R 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC TOP VIEW (PINS DOWN) 11 12 0.025 (0.63) 0.015 (0.38) 0.032 (0.81) 0.026 (0.66) 19 18 0.430 (10.92) 0.390 (9.91) 0.040 (1.01) 0.
