Datasheet

Data Sheet AD5749
Rev. B | Page 23 of 28
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy
environments, the AD5749 offers the option of error checking
based on an 8-bit (CRC-8) cyclic redundancy check. The device
controlling the AD5749 should generate an 8-bit frame check
sequence using the following polynomial:
C(x) = x
8
+ x
2
+ x
1
+ 1
This is added to the end of the data-word, and 24 data bits are
sent to the AD5749 before taking
SYNC
high. If the AD5749
receives a 24-bit data frame, it performs the error check
when
SYNC
goes high. If the check is valid, then the data is
written to the selected register. If the error check fails, the
FAULT pin goes low and Bit D3 of the status register is set.
After reading this register, this error flag is cleared
automatically and the FAULT pin goes high again.
Figure 34. PEC Error Checking Timing
SCLK
S
DI
N
SY
N
C
U
PDA
T
E O
N SY
NC
HIG
H
D
1
5
(MSB)
D
0
(
LS
B)
16
-B
I
T DATA
16
-B
IT
DA
TA
TRAN
SFE
R—
NO
E
RRO
R
CHE
CKI
N
G
SCLK
SDIN
SYNC
FAULT
UPDATE AFTER SYNC
H
IGH
ONLY IF ERROR CHECK PASSED
F
AU
LT GO
ES LOW IF
ERROR CHECK FAILS
D23
(MSB)
D
8
(LSB)
D7
D0
16-BIT DA
TA
8
-B
IT
F
CS
16
-B
IT
DA
TA
TRAN
SFER WITH ERROR CHECKING
08923-035