Datasheet

AD5735 Data Sheet
Rev. C | Page 40 of 48
ASYNCHRONOUS CLEAR
CLEAR is an active high, edge sensitive input that allows the
output to be cleared to a preprogrammed 12-bit code. This code
is user-programmable via a per-channel 12-bit clear code register.
For a channel to be cleared, set the CLR_EN bit in the DAC
control register for that channel. If the clear function on a
channel is not enabled, the output remains in its current state,
independent of the level of the CLEAR pin.
When the CLEAR signal returns low, the relevant outputs remain
cleared until a new value is programmed to them.
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environ-
ments, the AD5735 offers the option of packet error checking
based on an 8-bit cyclic redundancy check (CRC-8). The device
controlling the AD5735 should generate an 8-bit frame check
sequence using the following polynomial:
C(x) = x
8
+ x
2
+ x
1
+ 1
This value is added to the end of the data-word, and 32 bits are
sent to the AD5735 before
SYNC
goes high. If the AD5735 sees a
32-bit frame, it performs the error check when
SYNC
goes high.
If the error check is valid, the data is written to the selected register.
If the error check fails, the
FAULT
pin goes low and the PEC error
bit in the status register is set. After the status register is read,
FAULT
returns high (assuming that there are no other faults),
and the PEC error bit is cleared automatically. It is not
recommended to tie both AD1 and AD0 low as a short low on
SDIN could possibly lead to a zero-scale update for DAC A.
SDIN
SYNC
SCLK
UPD
A
TE ON SYNC HIGH
MSB
D23
LSB
D0
24-BIT D
ATA
24-BIT DATA TRANSFER—NO ERROR CHECKING
SDIN
FAUL
T
SYNC
SCLK
UPD
ATE ON SYNC HIGH
ONL
Y IF ERROR CHECK PASSED
FAULT PIN GOES LOW
IF ERROR CHECK FAILS
MSB
D31
LSB
D8
D7 D0
24-BIT DATA
8-BIT CRC
32-BIT DATA TRANSFER WITH ERROR CHECKING
09961-180
Figure 76. PEC Timing
Packet error checking can be used for transmitting and receiving
data packets. If status readback during a write is enabled, the PEC
values returned during the status readback operation should be
ignored. If status readback during a write is disabled, the user
can still use the normal readback operation to monitor status
register activity with PEC.
WATCHDOG TIMER
When enabled, an on-chip watchdog timer generates an alert
signal if 0x195 is not written to the software register within the
programmed timeout period. This feature is useful to ensure
that communication has not been lost between the MCU and
the AD5735 and that the datapath lines are working properly
(that is, SDIN, SCLK, and
SYNC
). If 0x195 is not received by
the software register within the timeout period, the ALERT pin
signals a fault condition. The ALERT pin is active high and can
be connected directly to the CLEAR pin to enable a clear in the
event that communication from the MCU is lost.
To enable the watchdog timer and set the timeout period (5 ms,
10 ms, 100 ms, or 200 ms), program the main control register
(see Table 21 and Table 22).
ALERT OUTPUT
The AD5735 is equipped with an ALERT pin. This pin is an
active high CMOS output. The AD5735 also has an internal
watchdog timer. When enabled, the watchdog timer monitors
SPI communications. If 0x195 is not received by the software
register within the timeout period, the ALERT pin is activated.
INTERNAL REFERENCE
The AD5735 contains an integrated 5 V voltage reference with
initial accuracy of ±5 mV maximum and a temperature coefficient
of ±10 ppm/°C maximum. The reference voltage is buffered
and is externally available for use elsewhere within the system.
REFOUT must be connected to REFIN to use the internal
reference.
EXTERNAL CURRENT SETTING RESISTOR
R
SET
is an internal sense resistor that is part of the voltage-to-
current conversion circuitry (see Figure 71). The stability of the
output current value over temperature is dependent on the stability
of the R
SET
value. To improve the stability of the output current
over temperature, the internal R
SET
resistor, R1, can be bypassed
and an external, 15 kΩ, low drift resistor can be connected to
the R
SET_x
pin of the AD5735. The external resistor is selected
via the DAC control register (see Table 24).
Table 1 provides the performance specifications for the AD5735
with both the internal R
SET
resistor and an external, 15 kΩ R
SET
resistor. The use of an external R
SET
resistor allows for improved
performance over the internal R
SET
resistor option. The external
R
SET
resistor specifications assume an ideal resistor; the actual
performance depends on the absolute value and temperature
coefficient of the resistor used. This directly affects the gain error
of the output and, thus, the total unadjusted error. To arrive at
the gain/TUE error of the output with a specific external R
SET
resistor, add the absolute error percentage of the R
SET
resistor
directly to the gain/TUE error of the AD5735 with the external
R
SET
resistor, as shown in Table 1 (expressed in % FSR).